SLUSE50 November 2023 TPS92642-Q1
PRODUCTION DATA
- 1
- 1 Features
- 2 Applications
- 3 Description
- 4 Pin Configuration and Functions
- 5 Specifications
-
6 Detailed Description
- 6.1 Overview
- 6.2 Functional Block Diagram
- 6.3
Feature Description
- 6.3.1 Internal Regulator
- 6.3.2 Buck Converter Switching Operation
- 6.3.3 Bootstrap Supply
- 6.3.4 Switching Frequency and Adaptive On-Time Control
- 6.3.5 Minimum On-Time, Off-Time, and Inductor Ripple
- 6.3.6 LED Current Regulation and Error Amplifier
- 6.3.7 Start-Up Sequence
- 6.3.8 Analog Dimming and Forced Continuous Conduction Mode
- 6.3.9 External PWM Dimming and Input Undervoltage Lockout (UVLO)
- 6.3.10 Pulse Duty Cycle Limit Circuit
- 6.3.11 Output Short and Open-Circuit Faults
- 6.3.12 Overcurrent Protection
- 6.3.13 Thermal Shutdown
- 6.3.14 Fault Indicator and Diagnostics Summary
- 6.4 Device Functional Modes
-
7 Application and Implementation
- 7.1
Application Information
- 7.1.1 Duty Cycle Considerations
- 7.1.2 Switching Frequency Selection
- 7.1.3 LED Current Programming
- 7.1.4 Inductor Selection
- 7.1.5 Output Capacitor Selection
- 7.1.6 Input Capacitor Selection
- 7.1.7 Bootstrap Capacitor Selection
- 7.1.8 Compensation Capacitor Selection
- 7.1.9 Input Dropout and Undervoltage Protection
- 7.1.10 Pulse Duty Cycle Limit Circuit
- 7.1.11 Protection Diodes
- 7.2
Typical Application
- 7.2.1 Design Requirements
- 7.2.2
Detailed Design Procedure
- 7.2.2.1 Calculating Duty Cycle
- 7.2.2.2 Calculating Minimum On-Time and Off-Time
- 7.2.2.3 Minimum Switching Frequency
- 7.2.2.4 LED Current Set Point
- 7.2.2.5 Inductor Selection
- 7.2.2.6 Output Capacitor Selection
- 7.2.2.7 Bootstrap Capacitor Selection
- 7.2.2.8 Compensation Capacitor Selection
- 7.2.2.9 VIN Dropout Protection and PWM Dimming
- 7.2.3 Application Curves
- 7.3 Power Supply Recommendations
- 7.4 Layout
- 7.1
Application Information
- 8 Device and Documentation Support
- 9 Revision History
- 10Mechanical, Packaging, and Orderable Information
6.3.2 Buck Converter Switching Operation
The following operating description of the TPS92642-Q1 refers to the Functional Block Diagram and the waveforms in Figure 6-1. The main control loop of the TPS92642-Q1 is based on an adaptive on-time pulse width modulation (PWM) technique that combines a constant on-time control with an inductor valley current sense circuit for pseudo-fixed frequency operation. This proprietary control technique enables closed-loop regulation of LED current and fast dynamic response necessary to meet the requirements for driver monitoring systems (DMS) using infrared and laser diodes.
Figure 6-1 Adaptive On-Time Buck
Converter WaveformsIn steady state, the high-side MOSFET is turned on at the beginning of each cycle. The on-time duration of this MOSFET is controlled by an internal one-shot timer and the high-side MOSFET is turned off after the timer expires. The one-shot timer duration is set by the output voltage measured at the CSP pin, VCSP, and the input voltage measured at the VIN pin, VIN, to maintain a pseudo-fixed frequency. During the on-time interval, the inductor current increases with a slope proportional to the voltage applied across its terminals (VIN – VCSP).
The low-side MOSFET is turned on after a fixed dead time and the inductor current then decreases with the constant slope proportional to the output voltage, VCSP. Inductor current measured by the external sense resistor is compared to the valley threshold, VVAL, by an internal high-speed comparator. This MOSFET is turned off and the one-shot timer is initiated when the sensed inductor current falls below the valley threshold voltage. The high-side MOSFET is turned on again after a fixed dead time.
The internal rail-to-rail error amplifier sets the valley threshold voltage and regulates the average inductor current based on a reference value set by VIADJ pin. A simple integral loop compensation circuit consisting of a capacitor connected from the COMP pin to GND provides a stable and high-bandwidth response. As the inductor current is directly sensed by an external resistor, the device operation is not sensitive to the ESR of the output capacitors and is compatible with common multilayered ceramic capacitors (MLCC).