SLUSE50 November   2023 TPS92642-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Internal Regulator
      2. 6.3.2  Buck Converter Switching Operation
      3. 6.3.3  Bootstrap Supply
      4. 6.3.4  Switching Frequency and Adaptive On-Time Control
      5. 6.3.5  Minimum On-Time, Off-Time, and Inductor Ripple
      6. 6.3.6  LED Current Regulation and Error Amplifier
      7. 6.3.7  Start-Up Sequence
      8. 6.3.8  Analog Dimming and Forced Continuous Conduction Mode
      9. 6.3.9  External PWM Dimming and Input Undervoltage Lockout (UVLO)
      10. 6.3.10 Pulse Duty Cycle Limit Circuit
      11. 6.3.11 Output Short and Open-Circuit Faults
      12. 6.3.12 Overcurrent Protection
      13. 6.3.13 Thermal Shutdown
      14. 6.3.14 Fault Indicator and Diagnostics Summary
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1  Duty Cycle Considerations
      2. 7.1.2  Switching Frequency Selection
      3. 7.1.3  LED Current Programming
      4. 7.1.4  Inductor Selection
      5. 7.1.5  Output Capacitor Selection
      6. 7.1.6  Input Capacitor Selection
      7. 7.1.7  Bootstrap Capacitor Selection
      8. 7.1.8  Compensation Capacitor Selection
      9. 7.1.9  Input Dropout and Undervoltage Protection
      10. 7.1.10 Pulse Duty Cycle Limit Circuit
      11. 7.1.11 Protection Diodes
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Calculating Duty Cycle
        2. 7.2.2.2 Calculating Minimum On-Time and Off-Time
        3. 7.2.2.3 Minimum Switching Frequency
        4. 7.2.2.4 LED Current Set Point
        5. 7.2.2.5 Inductor Selection
        6. 7.2.2.6 Output Capacitor Selection
        7. 7.2.2.7 Bootstrap Capacitor Selection
        8. 7.2.2.8 Compensation Capacitor Selection
        9. 7.2.2.9 VIN Dropout Protection and PWM Dimming
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Compact Layout for EMI Reduction
          1. 7.4.1.1.1 Ground Plane
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
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订购信息

6.1 Overview

The TPS92642-Q1 is a wide input, synchronous buck LED driver. The device can deliver up to 5 A of continuous current and power a single string of one to 10 series-connected LEDs. The device implements an adaptive on-time current regulation control technique to achieve fast transient response. This architecture uses a comparator and a one-shot on-timer that varies inversely with input and output voltage to maintain a near-constant frequency. The integrated low offset rail-to-rail error amplifier enables closed-loop regulation of LED current and ensures better than 4% accuracy over a wide input, output, and temperature range. The LED current reference is set by the IADJ pin and is programmed by a voltage divider to achieve over a 15:1 linear analog dimming range. The high impedance IADJ input simplifies LED current binning and thermal protection.

The TPS92642-Q1 device incorporates an internal pulse generator to implement a maximum LED pulse duty cycle limit. The maximum PWM duty cycle, DPLMT, is internally fixed to 13.6% (typical) of the PWM period. This PWM period is set using external capacitor, CPLMT, connected from the PLMT pin to GND. The LED current can be pulse width modulated by the external pulsed signal connected to the UDIM input for any duration less than the limit, tPWM_ON(LMT), set by the internal pulse generator circuit. The maximum on-time, tPWM_ON(LMT)is fixed at DPLMT × tPLMT where tPLMT is the period set by the external CPLMT capacitor. In addition, the internal pulse generator also behaves as a one-shot timer and blocks any subsequent UDIM pulses until the end of the period, tPLMT. The internal pulse generator circuit and maximum duty cycle limit function can be disabled by connecting PLMT pin to GND. This device optimizes the inductor current response and is capable of responding to an input PWM signal with a minimum pulse width of 10 µs.

The device incorporates enhanced fault features, including the following:

  • Cycle-by-cycle switch overcurrent limit
  • Input undervoltage protection
  • Boot undervoltage protection
  • Comp overvoltage warning
  • LED short-circuit indication

In addition, thermal shutdown (TSD) protection is implemented to limit the junction temperature at 175°C (typical).
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