SLUSE50 November   2023 TPS92642-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Internal Regulator
      2. 6.3.2  Buck Converter Switching Operation
      3. 6.3.3  Bootstrap Supply
      4. 6.3.4  Switching Frequency and Adaptive On-Time Control
      5. 6.3.5  Minimum On-Time, Off-Time, and Inductor Ripple
      6. 6.3.6  LED Current Regulation and Error Amplifier
      7. 6.3.7  Start-Up Sequence
      8. 6.3.8  Analog Dimming and Forced Continuous Conduction Mode
      9. 6.3.9  External PWM Dimming and Input Undervoltage Lockout (UVLO)
      10. 6.3.10 Pulse Duty Cycle Limit Circuit
      11. 6.3.11 Output Short and Open-Circuit Faults
      12. 6.3.12 Overcurrent Protection
      13. 6.3.13 Thermal Shutdown
      14. 6.3.14 Fault Indicator and Diagnostics Summary
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1  Duty Cycle Considerations
      2. 7.1.2  Switching Frequency Selection
      3. 7.1.3  LED Current Programming
      4. 7.1.4  Inductor Selection
      5. 7.1.5  Output Capacitor Selection
      6. 7.1.6  Input Capacitor Selection
      7. 7.1.7  Bootstrap Capacitor Selection
      8. 7.1.8  Compensation Capacitor Selection
      9. 7.1.9  Input Dropout and Undervoltage Protection
      10. 7.1.10 Pulse Duty Cycle Limit Circuit
      11. 7.1.11 Protection Diodes
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Calculating Duty Cycle
        2. 7.2.2.2 Calculating Minimum On-Time and Off-Time
        3. 7.2.2.3 Minimum Switching Frequency
        4. 7.2.2.4 LED Current Set Point
        5. 7.2.2.5 Inductor Selection
        6. 7.2.2.6 Output Capacitor Selection
        7. 7.2.2.7 Bootstrap Capacitor Selection
        8. 7.2.2.8 Compensation Capacitor Selection
        9. 7.2.2.9 VIN Dropout Protection and PWM Dimming
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Compact Layout for EMI Reduction
          1. 7.4.1.1.1 Ground Plane
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

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4 Pin Configuration and Functions

GUID-20200528-SS0I-1MR8-ZL66-Q6TQP9FBK1GH-low.gif Figure 4-1 PWP Package, 16-Pin HTSSOP with PowerPAD, Top View
Table 4-1 Pin Functions
PIN I/O DESCRIPTION
NO. NAME

7

AGND

 — Analog ground. Return for the internal voltage reference and analog circuit. Connect to circuit ground, GND, to complete return path.

3

BST

I

 Supply input for high-side MOSFET gate drive circuit. Connect a ceramic capacitor between BST and SW pins. An internal diode is connected between VCC and BST pins.

6

COMP

O

 Output of internal transconductance error amplifier. Connect an integral compensation network to ensure stability.

10

 CSN I Negative input (–) of internal rail-to-rail transconductance error amplifier. Connect directly to the negative node of the LED current sense resistor, RCS.

11

 CSP I Positive input (+) of internal rail-to-rail transconductance error amplifier. Connect directly to the positive node of the LED current sense resistor, RCS.

9

 FLT

O

 Open-drain fault indicator. Connect to VCC with a resistor to create an active low fault signal output.

5

 IADJ

I

 Analog adjust input. Input below 100 mV disables the output. The analog input can be varied between 140 mV to 2.4 V to set current reference from 10 mV to 175 mV. Connect a 0.1-μF capacitor from pin to AGND.

16

PGND

 — Ground returns for low-side MOSFETs

8

 PLMT

I

 Pulse limit pin. Connect a capacitor from the PLMT pin to GND to set minimum period allowed of the external PWM pulse.

13

RON

I

 On-time programming pin. Connect a resistor to VIN based on the desired pseudo-fixed switching frequency.
1,2 SW I Switching output of the regulator. Internally connected to both power MOSFETs. Connect to the power inductor.

12

 UDIM

I

 Undervoltage lockout and external PWM dimming input. Connect to VIN through a resistor divider to implement input undervoltage protection. Diode couple external PWM signal to enable dimming. Do not float.
4 VCC O VCC bias supply pin. Locally decouple to AGND using a 2.2-μF to 4.7-μF ceramic capacitor located close to the controller.
14,15 VIN I Power input and connection to high-side MOSFET drain node. Connect to the power supply and bypass capacitors CIN. The path from the VIN pin to the high frequency bypass capacitor and PGND must be as short as possible.
PowerPAD — The AGND and PGND pin must be connected to the exposed PowerPAD for proper operation. This PowerPAD must be connected to PCB ground plane using multiple vias for good thermal performance.
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