SLUSE50 November   2023 TPS92642-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Internal Regulator
      2. 6.3.2  Buck Converter Switching Operation
      3. 6.3.3  Bootstrap Supply
      4. 6.3.4  Switching Frequency and Adaptive On-Time Control
      5. 6.3.5  Minimum On-Time, Off-Time, and Inductor Ripple
      6. 6.3.6  LED Current Regulation and Error Amplifier
      7. 6.3.7  Start-Up Sequence
      8. 6.3.8  Analog Dimming and Forced Continuous Conduction Mode
      9. 6.3.9  External PWM Dimming and Input Undervoltage Lockout (UVLO)
      10. 6.3.10 Pulse Duty Cycle Limit Circuit
      11. 6.3.11 Output Short and Open-Circuit Faults
      12. 6.3.12 Overcurrent Protection
      13. 6.3.13 Thermal Shutdown
      14. 6.3.14 Fault Indicator and Diagnostics Summary
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1  Duty Cycle Considerations
      2. 7.1.2  Switching Frequency Selection
      3. 7.1.3  LED Current Programming
      4. 7.1.4  Inductor Selection
      5. 7.1.5  Output Capacitor Selection
      6. 7.1.6  Input Capacitor Selection
      7. 7.1.7  Bootstrap Capacitor Selection
      8. 7.1.8  Compensation Capacitor Selection
      9. 7.1.9  Input Dropout and Undervoltage Protection
      10. 7.1.10 Pulse Duty Cycle Limit Circuit
      11. 7.1.11 Protection Diodes
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Calculating Duty Cycle
        2. 7.2.2.2 Calculating Minimum On-Time and Off-Time
        3. 7.2.2.3 Minimum Switching Frequency
        4. 7.2.2.4 LED Current Set Point
        5. 7.2.2.5 Inductor Selection
        6. 7.2.2.6 Output Capacitor Selection
        7. 7.2.2.7 Bootstrap Capacitor Selection
        8. 7.2.2.8 Compensation Capacitor Selection
        9. 7.2.2.9 VIN Dropout Protection and PWM Dimming
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Compact Layout for EMI Reduction
          1. 7.4.1.1.1 Ground Plane
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
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订购信息

5.5 Electrical Characteristics

–40°C < TJ < 150°C, VIN = 14V, VUDIM = 5V, VIADJ = 2.1V, CVCC = 2.2μF, CBST = 1nF, CCOMP = 1nF, RCS = 100mΩ, RON = 401kΩ, , CPLMT = 680nF, fSW = 200 kHz
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT VOLTAGE (VIN)
VDO LDO dropout voltage IVCC = 20 mA, VVIN = 5 V 315 mV
ISW Input switching current 10 17.6 mA
IOP Input operating current Not switching, VIADJ = VVCC 2 4 mA
BIAS SUPPLY (VCC)
VCC(UVLO-RISE) Rising threshold VCC rising threshold, VVIN = 8 V 4.40 4.58 V
VCC(UVLO-FALL) Falling threshold VCC falling threshold, VVIN = 8 V 3.9 4.2 V
VCC(UVLO-HYS) Hysteresis 200 mV
VCC(REG) Regulation voltage No Load 4.75 5.00 5.25 V
ICC(LIMIT) Supply current Limit VVCC = 0 V 45 56 76 mA
HIGH-SIDE FET (SW, BOOT)
RDS(ON-HS) High-side MOSFET on resistance ILED = 100 mA 65 130 mΩ
VBST(UV) Bootstrap gate drive UVLO V(BST-SW) rising 3.24 3.4 3.54 V
VBST(HYS) Bootstrap gate drive UVLO hysteresis Hysteresis 175 207 240 mV
IQ(BST) Bootstrap pin quiescent current VSW = 0V, VUDIM = 0 V, VBOOT = 5 V 215 280 350 µA
LOW-SIDE FET (SW)
RDS(ON-LS) Low-side MOSFET on resistance ILED = 100 mA 67 130 mΩ
HIGH SIDE FET CURRENT LIMIT
ILIM(HS) High-side current limit threshold 6.1 8.6 10.3 A
t(HS-BLANK) High-side current sense blanking period 60 ns
LOW SIDE FET CURRENT LIMIT
ISINK(LS) Sinking current limit 2.0 3.2 4.3 A
tBLANK Blanking time 71 ns
ERROR AMPLIFIER (CSP, CSN, COMP)
V(CSP-CSN) Current sense threshold VIADJ = VCC, VCSP = 3 V, ICOMP = 0 V 168 175 182 mV
VIADJ = 2.1 V, VCSP = 3 V, ICOMP = 0 V 150 mV
ICSP CSP bias current VIADJ = 150 mV 10 µA
gM Transconductance 450 µA/V
ICOMP(SRC) COMP current source capacity VIADJ = 2.5 V, V(CSP-CSN) = 0 V 200 µA
ICOMP(SINK) COMP current sink capacity VIADJ = 150 mV, V(CSP-CSN) = 300 mV 140 µA
VCOMP(RISE) COMP startup threshold Rising 2.45 V
VCOMP(HYS) COMP startup comparator hysteresis 440 mV
EA(BW) Bandwidth Unity gain bandwidth 3 MHz
ICOMP(LKG) Comp leakage current VUDIM = 0 V 2.5 nA
VCOMP(RST) COMP pin reset voltage VVCC dropping from 5 V to 0 V 100 mV
RCOMP(DCH) COMP discharge FET resistance 230 Ω
VCOMP(OV) COMP overvoltage protection threshold 2.9 3.2 V
VCOMP(OV-HYS) COMP overvoltage protection hysteresis 60 mV
VCSP(SHORT) Output short circuit detection threshold Falling 1.5 V
Rising 1.6 V
ANALOG ADJUST INPUT (IADJ)
VIADJ(CLAMP) IADJ internal clamp voltage 2.45 V
VIADJ(DIS)
Disable threshold voltage

 Rising 133 mV
VIADJ(DIS) Disable threshold voltage Falling 100 mV
VALLEY CURRENT COMPARATOR
gM(LV) Level shift amplifier transconductance 50 µA/V
tDEL V(CSP-CSN) falling to gate rising delay 65 ns
ON-TIME GENERATOR (RON)
tON(MIN) Minimum on-time 85 101 117 ns
tON Programmed on-time VVIN = 14 V, VCSP = 5 V, RON = 35 kΩ 150 ns
VVIN = 10 V, VCSP = 8 V, RON = 35 kΩ 336 ns
VVIN = 14 V, VCSP = 3 V, RON = 400 kΩ 0.95 µs
VVIN = 10 V, VCSP = 8 V, RON = 400 kΩ 3.55 µs
MINIMUM OFF-TIME
tOFF(MIN) Minimum off-time V(CSP-CSN) = 0 V, VCOMP = 2.5 V 63 78 93 ns
PWM DIMMING and PROGRAMMABLE UVLO INPUT (UDIM)
IUDIM(DO) UDIM source current (UVLO hysteresis) VUDIM > 2.45 V 6.5 10 13 µA
VUDIM(EN,RISE) Undervoltage lockout rising threshold VUDIM rising 1.22 1.27 V
VUDIM(EN,FALL) Undervoltage lockout falling threshold VUDIM falling 1.075 1.120 V
tUDIM(RISE) UDIM to SW pin rising delay 1200 ns
tUDIM(FALL) UDIM pin SW pin falling delay 105 ns
DUTY CYCLE LIMIT
RPLMT(PU) PLMT Pull-Up Resistor 19.2 22.7 28.3 kΩ
RPLMT(PD) PLMT Pull-Down Resistor 75.0 91.8 110.0 kΩ
RPLMT(DIS) PLMT Discharge Resistor 48 Ω
VPLMT(PK) PLMT Peak Voltage 2.340 2.439 2.540 V
VPLMT(VAL) PLMT Valley Voltage 786 819 851 mV
FAULT INDICATION (nFLT)
R(FLT) Fault pin pull-down resistance IFLT = 20 mA 2.5 7 Ω
TOC Hiccup retry delay time 5.5 ms
TUC(BLANK) Undercurrent reporting blanking period 20 µs
IFLT(LKG) Fault pin leakage current 100 nA
THERMAL SHUTDOWN
TSD Thermal shutdown threshold 175 °C
TSD(HYS) Thermal shutdown hysteresis 15 °C
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