In order to ensure clean start-up, the TPS929121-Q1 uses UVLO and POR circuitry to clear its internal registers upon power-up and to reset registers with its default values.

The TPS929121-Q1 has internal UVLO circuits so that when either power supply voltage V_(SUPPLY) or LDO output voltage V_(LDO) is lower than its UVLO threshold, POR is triggered. In POR state, the device resets digital core and all registers to default value. FLAG_POR register is set to 1 for each POR cycle to indicate the POR history.

Before both powers are above UVLO thresholds, the TPS929121-Q1 stays in POR state with all outputs off and ERR pulled down. Once both power supplies are above UVLO threshold, the device enters INIT mode for initialization releasing ERR pulldown. A programmable timer starts counting in INIT state, the timer length can be set by EEPROM register EEP_INITTIMER. When the timer is completed, the device switches to normal state. In INIT state, setting CLR_POR to 1 clears FLAG_POR, disables the timer, and sets the device to normal state.

Upon powering up, the TPS929121-Q1 automatically loads all settings stored in EEPROM to correlated registers and sets the other registers to default value which don't have correlated EEPROM. All channels are powered up in off-state by default to avoid unwanted blinking.

Writing 1 to CLR_REG manually loads EEPROM setting to the correlated registers and set the other registers to default value. After CLR_REG is set, the FLAG_POR is set 1 to indicate registers clear to default values. Writing 1 to CLR_POR resets the FLAG_POR register to 0. TI recommends settting CLR_REG to 1 to clear the internal registers every time after POR. The CLR_REG automatically resets to 0.