The TPS929121-Q1 with FlexWire protocol supports burst mode for multiple data bytes writing and reading in one data transaction cycle to accelerate the communication between the master controller and slaves. Figure 8-16 shows the data format for multiple data bytes write, and Figure 8-17 shows the data format for multiple data bytes read. The DATA_1 is written to the register in REG_ADDR address, and the following DATA_2 to DATA_N are written to the registers in REG_ADDR+1 to REG_ADDR+N address sequentially for multiple bytes write. For multiple data read, the DATA_1 is read from the register in REG_ADDR address, and the following DATA_2 to DATA_N are read from the registers in REG_ADDR+1 to REG_ADDR+N address sequentially.

Figure 8-16 Multiple Data Bytes Write in Burst Mode

Figure 8-17 Multiple Data Bytes Read in Burst Mode