ZHCSLS0B July 2022 – April 2024 TPS929240-Q1
PRODUCTION DATA
请参考 PDF 数据表获取器件具体的封装图。
The INITIALIZATION state is designed to allow master controller to have enough time to power up before the device automatically gets into FAIL-SAFE states. INIT mode has a configurable delay programmed by 4-bit register INITTIMER. After the delay counter is reached, the device changes to NORMAL state. In INIT state, the communication between master controller and the TPS929240-Q1 is enabled through FlexWire interface. In INITIALIZATION state, device automatically load register map default values, which can be programmed in corresponding EEPROM. The master controller sets CLRPOR to 1 in INITIALIZATION state, the device immediately switches to NORMAL state. Only write CLRPOR to TPS929240-Q1 in INITIALIZATION state.