ZHCSIF5G December 2015 – July 2024 TPS99000-Q1
PRODUCTION DATA
The TPS99000-Q1 includes four low drop out regulators, dedicated to specific internal functions:
The positive output LDO regulators are all designed to operate from the same nominal 6V input as is needed by the LED selection FET gate driver supply input, DRVR_PWR, and the DMD mirror voltage regulator, VIN_DRST. However, care must be taken to isolate the sensitive analog circuit power supply inputs from switching noise, through dedicated sub-planes and supply filtering techniques. Noise on the analog supply rails will directly impact system dimming range performance, limiting stable operation at low brightness levels.
The negative 8V LDO is designed to use the DMD_VRESET power rail as its power source. (Note that this usage implies that the TIA/photodiode path will not be available for use until the DMD is in a powered-up state.)
Applications that do not use a photodiode do not require the -8V regulator. VLDOT_M8 and VIN_LDOT_M8 may be left disconnected if the option in the DLPC230 SW to prevent enabling of the –8V LDO is selected. If these pins are not connected, care must be taken to confirm that the -8V LDO is not enabled. If this regulator is enabled while the pins are disconnected, permanent damage may be caused to the device.