ZHCSN32B June   2019  – July 2024 TPS99001-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics—Analog to Digital Converter
    6. 5.6  Electrical Characteristics—Voltage Regulators
    7. 5.7  Electrical Characteristics—Temperature and Voltage Monitors
    8. 5.8  Electrical Characteristics—Current Consumption
    9. 5.9  Power-Up Timing Requirements
    10. 5.10 Power-Down Timing Requirements
    11. 5.11 Timing Requirements—Sequencer Clock
    12. 5.12 Timing Requirements—Host and Diagnostic Port SPI Interface
    13. 5.13 Timing Requirements—ADC Interface
    14. 5.14 Switching Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog to Digital Converter
        1. 6.3.1.1 Analog to Digital Converter Input Table
      2. 6.3.2 Power Sequencing and Monitoring
        1. 6.3.2.1 Power Monitoring
      3. 6.3.3 DMD Mirror Voltage Regulator
      4. 6.3.4 Low Dropout Regulators
      5. 6.3.5 System Monitoring Features
        1. 6.3.5.1 Windowed Watchdog Circuits
        2. 6.3.5.2 Die Temperature Monitors
        3. 6.3.5.3 External Clock Ratio Monitor
      6. 6.3.6 Communication Ports
        1. 6.3.6.1 Serial Peripheral Interface (SPI)
    4. 6.4 Device Functional Modes
      1. 6.4.1 OFF
      2. 6.4.2 STANDBY
      3. 6.4.3 POWERING_DMD
      4. 6.4.4 DISPLAY_RDY
      5. 6.4.5 PARKING
      6. 6.4.6 SHUTDOWN
    5. 6.5 Register Maps
      1. 6.5.1 System Status Registers
      2. 6.5.2 ADC Control
      3. 6.5.3 General Fault Status
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Headlight
        1. 7.2.1.1 Design Requirements
  9. 8 Power Supply Recommendations
    1. 8.1 TPS99001-Q1 Power Supply Architecture
    2. 8.2 TPS99001-Q1 Power Outputs
    3. 8.3 Power Supply Architecture
  10. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Power/High Current Signals
      2. 9.1.2 Sensitive Analog Signals
      3. 9.1.3 High-Speed Digital Signals
      4. 9.1.4 Kelvin Sensing Connections
      5. 9.1.5 Ground Separation
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 第三方米6体育平台手机版_好二三四免责声明
    2. 10.2 接收文档更新通知
    3. 10.3 支持资源
    4. 10.4 Trademarks
    5. 10.5 静电放电警告
    6. 10.6 术语表
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5.10 Power-Down Timing Requirements

See (1)

MIN MAX UNIT
tvhold1 Host voltage hold time after VMAIN minimum threshold reached.
tmon4(max) + tpark(max) + tw2(max)		 VMAIN threshold to 6V and 3.3V power loss(2)(3) 900 μs
tvhold2 Host voltage hold time after PROJ_ON deasserted.
tmon5(max) + tpark(max) + tw2(max)		 VMAIN threshold to 6V and 3.3V power loss.(2)(3) 1.78 ms
tmon4 VMAIN monitoring time Minimum voltage trip threshold to PARKZ falling edge 52 120 μs
tmon5 PROJ_ON deassertion reaction time Falling edge of PROJ_ON to PARKZ falling edge 1 ms
tpark DMD Park time PARKZ falling edge to start DMD_VOFFSET discharge 280 μs
tdischarge(4) DMD voltage rail discharge time VOFFSET Cout = 1μF
VRESET Cout = 1μF
VBIAS Cout = 0.47μF		 260 μs
tw2 DMD voltage disables to RESETZ deassertion Start of DMD voltage rail discharge to RESETZ falling edge 500 μs
(1) There are two methods for initiating the power-down sequence:
  1. VMAIN voltage decreases below its minimum threshold. This is typical if the TPS99001-Q1 is expected to initiate the power-down sequence when the main power is removed from the system. Note that the 6V and 3.3V input rails must remain within the operating range for a specified period of time after the power-down sequence begins.
  2. PROJ_ON low. This allows a host controller to initiate power down through a digital input to the TPS99001-Q1.
(2) 6V input rails include DRVR_PWR, VIN_DRST, VIN_LDOT_5V, VIN_LDOA_3P3V, VIN_LDOT3P3V.
(3) 3.3V input rails include VDD_IO, DVDD, AVDD.
(4) The DMD specifies a maximum absolute voltage difference between VBIAS and VOFFSET. To remain below this maximum voltage difference, VBIAS must discharge faster than VOFFSET. This is accomplished by using a smaller Cout capacitance for VBIAS to allow it to discharge quicker than VOFFSET.
TPS99001-Q1 Power Down Timing—VMAIN Trigger Figure 5-2 Power Down Timing—VMAIN Trigger
TPS99001-Q1 Power Down Timing—PROJ_ON Trigger Figure 5-3 Power Down Timing—PROJ_ON Trigger
千亿体育app官网登录(中国)官方网站IOS/安卓通用版/手机APP | 米乐app下载官网（中国）|ios|Android/通用版APP最新版 | 米乐|米乐·M6（中国大陆）官方网站 | 千亿体育登陆地址 | 华体会体育（中国）HTH·官方网站 | 千赢qy国际_全站最新版千赢qy国际V6.2.14安卓/IOS下载 | 18新利网v1.2.5|中国官方网站 | bob电竞真人（中国官网）安卓/ios苹果/电脑版【1.97.95版下载】 | 千亿体育app官方下载(中国)官方网站IOS/安卓/手机APP下载安装 |