ZHCSN32B June   2019  – July 2024 TPS99001-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics—Analog to Digital Converter
    6. 5.6  Electrical Characteristics—Voltage Regulators
    7. 5.7  Electrical Characteristics—Temperature and Voltage Monitors
    8. 5.8  Electrical Characteristics—Current Consumption
    9. 5.9  Power-Up Timing Requirements
    10. 5.10 Power-Down Timing Requirements
    11. 5.11 Timing Requirements—Sequencer Clock
    12. 5.12 Timing Requirements—Host and Diagnostic Port SPI Interface
    13. 5.13 Timing Requirements—ADC Interface
    14. 5.14 Switching Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog to Digital Converter
        1. 6.3.1.1 Analog to Digital Converter Input Table
      2. 6.3.2 Power Sequencing and Monitoring
        1. 6.3.2.1 Power Monitoring
      3. 6.3.3 DMD Mirror Voltage Regulator
      4. 6.3.4 Low Dropout Regulators
      5. 6.3.5 System Monitoring Features
        1. 6.3.5.1 Windowed Watchdog Circuits
        2. 6.3.5.2 Die Temperature Monitors
        3. 6.3.5.3 External Clock Ratio Monitor
      6. 6.3.6 Communication Ports
        1. 6.3.6.1 Serial Peripheral Interface (SPI)
    4. 6.4 Device Functional Modes
      1. 6.4.1 OFF
      2. 6.4.2 STANDBY
      3. 6.4.3 POWERING_DMD
      4. 6.4.4 DISPLAY_RDY
      5. 6.4.5 PARKING
      6. 6.4.6 SHUTDOWN
    5. 6.5 Register Maps
      1. 6.5.1 System Status Registers
      2. 6.5.2 ADC Control
      3. 6.5.3 General Fault Status
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Headlight
        1. 7.2.1.1 Design Requirements
  9. 8 Power Supply Recommendations
    1. 8.1 TPS99001-Q1 Power Supply Architecture
    2. 8.2 TPS99001-Q1 Power Outputs
    3. 8.3 Power Supply Architecture
  10. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Power/High Current Signals
      2. 9.1.2 Sensitive Analog Signals
      3. 9.1.3 High-Speed Digital Signals
      4. 9.1.4 Kelvin Sensing Connections
      5. 9.1.5 Ground Separation
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 第三方米6体育平台手机版_好二三四免责声明
    2. 10.2 接收文档更新通知
    3. 10.3 支持资源
    4. 10.4 Trademarks
    5. 10.5 静电放电警告
    6. 10.6 术语表
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

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4 Pin Configuration and Functions

TPS99001-Q1 PZP Package100-Pin HTQFPTop View Figure 4-1 PZP Package100-Pin HTQFPTop View
Table 4-1 Pin Functions—Initialization, Clock, and Diagnostics
PIN TYPE DESCRIPTION
NO. NAME
6 WD1 I Watchdog interrupt channel 1
7 WD2 I Watchdog interrupt channel 2
8 PARK_Z O DMD mirror parking signal (active low)
9 RESET_Z O Reset output to the DLPC23x-Q1. TPS99001-Q1 controlled.
10 INT_Z O Interrupt output signal to DLPC23x-Q1 (open drain). Recommended to pull up to the DLPC23x-Q1 3.3V rail controlled by the TPS99001-Q1's ENB_3P3V signal.
11 PROJ_ON I Input signal to enable/disable the IC and DLP projector
16 SEQ_START I PWM shadow latch control; indicates a start of sequence
17 SEQ_CLK I Sequencer clock
40 DMUX0 O Digital test point output
41 DMUX1 O Digital test point output
57 AMUX1 O Analog test mux output 1
61 AMUX0 O Analog test mux output 0
Table 4-2 Pin Functions—Power and Ground
PIN TYPE DESCRIPTION
NO. NAME
13, 35 VSS_IO GND Ground connection for digital IO interface
14, 36 VDD_IO POWER 3.3V power input for IO rail supply
24 DVSS GND Digital core ground return
25, 60, 75, 99 PBKG GND Substrate tie and ESD ground return
26 DVDD POWER 3.3V power input for digital core supply
42 DRVR_PWR POWER 6V power input
48 VSS_DRVR GND Ground connection for driver power
49 DMD_VOFFSET POWER VOFFSET output rail. Connect a 1μF ceramic capacitor to ground
50 DMD_VBIAS POWER VBIAS output rail. Connect a 0.47μF ceramic capacitor to ground
51 DMD_VRESET POWER VRESET output rail. Connect a 1μF ceramic capacitor to ground. Connect to DRST_HS_IND through external diode. Connect anode of diode to DMD_VRESET.
53 DRST_PGND GND Power ground for DMD power supply. Connect to ground plane
55 VIN_DRST POWER 6V input for DMD power supply
56 VSS_DRST GND Ground supply for DMD power supply
59 AVDD POWER 3.3V power supply input for analog circuit
63 VLDOT_M8 POWER Unused. Leave open or unconnected.
64 VLDOT_5V POWER Filter cap interface for 5V LDO
65 VIN_LDOT_5V POWER 6V power input for 5V LDO
66 GND_LDO GND Power ground return for LDO
67 VIN_LDOT_3P3V POWER 6V power input for 3.3V LDO
68 VLDOT_3P3V POWER Filter cap interface for 3.3V LDO
71 VSS_TIA2 GND Ground
72 VSS_TIA1 GND Ground
78, 100 AVSS GND Analog ground
79 VIN_LDOA_3P3 POWER 6V power input for dedicated ADC interface 3.3V LDO supply
80 VLDOA_3P3 POWER Dedicated ADC interface 3.3V LDO filter cap output
81, 84, 87, 89, 91 VSSL_ADC GND External ADC channel bondwire and lead frame isolation ground
95 ADC_VREF POWER ADC reference voltage output
Table 4-3 Pin Functions—Power Supply Management
PIN TYPE DESCRIPTION
NO. NAME
1 ENB_1P1V O External 1.1V buck enable. 3.3V output
2 ENB_1P8V O External 1.8V buck enable. 3.3V output
3 ENB_3P3V O External 3.3V buck enable. 3.3V output
52 DRST_LS_IND ANA Connection for the DMD power supply inductor (10μH). Connect a 330pF, 50V capacitor to ground. X7R recommended
54 DRST_HS_IND ANA Connection for the DMD power supply inductor (10μH)
58 VMAIN I Main intermediate voltage monitor input. Use an external resistor divider to set voltage input for brownout monitoring.
62 VIN_LDOT_M8 O Unused. Leave open or unconnected.
96 V3P3V I External 3.3V buck voltage monitor input
97 V1P8V I External 1.8V buck voltage monitor input
98 V1P1V I External 1.1V buck voltage monitor input
Table 4-4 Pin Functions—Reserved Pins
PIN TYPE DESCRIPTION
NO. NAME
12 Reserved O Reserved. Leave unconnected.
15 Reserved O Reserved. Leave unconnected.
18 Reserved I Reserved. Connect to ground.
19 Reserved I Reserved. Connect to ground.
20 Reserved I Reserved. Connect to ground.
21 Reserved I Reserved. Connect to ground.
22 Reserved I Reserved. Connect to ground.
23 Reserved I Reserved. Connect to ground.
37 Reserved I Reserved. Connect to ground
38 Reserved O Reserved. Leave unconnected.
39 Reserved O Reserved. Leave unconnected.
43 Reserved O Reserved. Leave unconnected.
44 Reserved O Reserved. Leave unconnected.
45 Reserved O Reserved. Leave unconnected.
46 Reserved O Reserved. Leave unconnected.
47 Reserved O Reserved. Leave unconnected.
69 Reserved O Reserved. Leave unconnected.
70 Reserved I Reserved. Leave unconnected.
73 Reserved I Reserved. Leave unconnected.
74 Reserved O Reserved. Leave unconnected.
76 Reserved ANA Reserved. Connect to ground.
77 Reserved ANA Reserved. Connect to ground.
Table 4-5 Pin Functions—Serial Peripheral Interfaces
PIN TYPE DESCRIPTION
NO. NAME
27 SPI1_CLK I SPI control interface (DLPC23x-Q1 primary, TPS99001-Q1 secondary), clock input
28 SPI1_SS_Z I SPI control interface (DLPC23x-Q1 primary, TPS99001-Q1 secondary), chip select (active low)
29 SPI1_DOUT O SPI control interface (DLPC23x-Q1 primary, TPS99001-Q1 secondary), transmit data output
30 SPI1_DIN I SPI control interface (DLPC23x-Q1 primary, TPS99001-Q1 secondary), receive data input
31 SPI2_DIN I SPI diagnostic port (secondary), receive data input. For read-only monitoring
32 SPI2_DOUT O SPI diagnostic port (secondary), transmit data output. For read-only monitoring
33 SPI2_SS_Z I SPI diagnostic port (secondary), chip select (active low). For read-only monitoring
34 SPI2_CLK I SPI diagnostic port (secondary), clock input. For read-only monitoring
Table 4-6 Pin Functions—Analog to Digital Converter
PIN TYPE DESCRIPTION
NO. NAME
4 ADC_MISO O ADC 2-wire interface - data output. DLPC23x-Q1 primary, TPS99001-Q1 secondary.
5 ADC_MOSI I ADC 2-wire interface - data input. DLPC23x-Q1 primary, TPS99001-Q1 secondary.
82 LS_SENSE_N I Low side current sense ADC negative input, see Table 6-1
83 LS_SENSE_P I Low side current sense ADC positive input, see Table 6-1
85 ADC_IN1 I External ADC channel 1, see Table 6-1
86 ADC_IN2 I External ADC channel 2, see Table 6-1
88 ADC_IN3 I External ADC channel 3, see Table 6-1
90 ADC_IN4 I External ADC channel 4, see Table 6-1
92 ADC_IN5 I External ADC channel 5, see Table 6-1
93 ADC_IN6 I External ADC channel 6, see Table 6-1
94 ADC_IN7 I External ADC channel 7, see Table 6-1
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