The optional external gate driver
resistors, RGSRC and RGSNK, along with the diode are used
to:
- Limit ringing caused by parasitic
inductances and capacitances
- Limit ringing caused by high
voltage switching dv/dt, high current switching di/dt, and body-diode reverse
recovery
- Fine-tune gate drive strength for
sourcing and sinking
- Reduce electromagnetic
interference (EMI)
The TPSI3050 has a pullup structure with a P-channel MOSFET with a peak
source current of 1.5 A. Therefore, the peak source current can be predicted
with:
Equation 7.
where
- RGSRC: external
turn-on resistance.
- RDSON_VDRV: TPSI3050 driver on resistance in high state.
See Electrical Characteristics.
- VVDDH: VDDH voltage.
Assumed 10.2
V in this example.
- RGFET_INT: external
power transistor internal gate resistance, found in the power transistor data
sheet. Assume 0 Ω for this example.
- IO+: peak source
current. The minimum value between 1.5 A, the gate driver peak source current,
and the calculated value based on the gate drive loop resistance.
For this example,
RDSON_VDRV = 2.5Ω, RGSRC = 8 Ω,
and RGFET_INT = 0 Ω results in:
Equation 8.
Similarly, the TPSI3050 has a pulldown structure with an
N-channel MOSFET with a peak sink current of 3.0 A. Therefore, assuming
RGFET_INT = 0 Ω, the peak sink current can be predicted
with:
Equation 9.
where
- RGSRC: external
turn-on resistance.
- RGSNK: external
turn-off resistance.
- RDSON_VDRV: TPSI3050 driver on resistance in low state.
See Electrical Characteristics.
- VVDDH: VDDH voltage.
Assumed 10.2
V in this example.
- VF: diode forward
voltage drop. Assumed 0.7 V in this example.
- IO-: peak sink
current. The minimum value between 3.0 A, the gate driver peak sink current, and
the calculated value based on the gate drive loop resistance.
For this example, assuming RDSON_VDRV =
1.7 Ω, RGSRC = 8 Ω, RGSNK = 4.5 Ω, and
RGFET_INT = 0 Ω, results in:
Equation 10.
Importantly, the estimated peak
current is also influenced by PCB layout and load capacitance. Parasitic inductance
in the gate driver loop can slow down the peak gate drive current and introduce
overshoot and undershoot. Therefore, TI strongly recommends to minimize the gate
driver loop.