The C_DIV1 and C_DIV2 capacitors required depends on the amount of drop that can be tolerated on the VDDH rail during switching of the external load. The charge stored on the C_DIV1 and C_DIV2 capacitors is used to provide the current to the load during switching. During switching, charge sharing occurs and the voltage on VDDH drops. At a minimum, TI recommends that the total capacitance formed by the series combination of C_DIV1 and C_DIV2 be sized to be at least 30 times the total gate capacitance to be switched. This sizing results in an approximate 0.5V drop of the VDDH supply rail that is used to supply power to the VDRV signal. Equation 12 and Equation 13 can be to used to calculate the amount of capacitance required for a specified voltage drop.

C_DIV1 and C_DIV2 must be of the same type and tolerance.

where

• n is a real number greater than or equal to 3.0.
• C_DIV1 is the external capacitor from VDDH to VDDM.
• C_DIV2 is the external capacitor from VDDM to VSSS.
• Q_LOAD is the total charge of the load from VDRV to VSSS.
• ΔV is the voltage drop on VDDH when switching the load.

Larger values of ΔV can be used in the application, but excessive droop can cause the VDDH under-voltage lockout falling threshold (V_{VDDH_UVLO_F}) to be reached and cause VDRV to be asserted low. Note that as the series combination of C_DIV1 and C_DIV2 capacitance increases relative to Q_LOAD, the VDDH supply voltage drop decreases, but the initial charging of the VDDH supply voltage during power up increases.

For this design, a total gate charge for switching FET is 30nC. For a ΔV = 0.5V,

To reduce ΔV further, capacitances for this design were selected as: