The TPSI31P1-Q1 contains keep-off circuitry on the output driver. The purpose of the keep-off circuitry is to clamp the gate voltage below an acceptable level to prevent the external power switch from turning on when no power is present on the secondary rails. The keep-off circuitry can be used to replace or greatly reduce the requirements of an external bleed-off resistor on the external power switch.

Figure 6-3 shows a simplified schematic of the keep-off circuitry. Transistors MP1 and MN1 form the driver that provides the gate current to drive the external power switch (M1). When no power is available on the secondary, the 1MΩ resistor, is connected from the drain to gate of MN1, forming an NMOS diode configuration. Any external coupling into the VDRV signal, via the M1 parasitic gate-to-drain and gate-to-source capacitances, can cause the VDRV signal to rise. The diode configuration of MN1 sinks this current to keep VDRV from rising too high, clamping VDRV to V_{ACT_CLAMP} . This is sufficient to keep most power switches off. If desired, an additional resistance can also be placed (on the order of 250kΩ or higher) across the gate-to-source of M1. Note that any resistance applied requires power from the secondary supply in normal operation and must be accounted for in the overall power budget.

In addition to the MN1 diode clamp, the body diode of MP1 can also help absorb any coupling into VDRV. The equivalent capacitance, C_eq, which is the series combination of C_DIV1 and C_DIV2 is typically on the order of 100's of nanofarads for most applications. If power transfer has ceased for some time, this capacitance is fully discharged to VSSS and clamps VDRV a diode above VSSS via the body diode of MP1 connected to VDDH. Any external coupling into the VDRV signal, via the M1 parasitic gate-to-drain and gate-to-source capacitances, is absorbed by C_eq, minimizing the voltage rise on VDRV.

Figure 6-3 Keep-off Circuitry