The TPSI31P1-Q1 includes two identical isolated comparators. A simplified block diagram is shown in Figure 6-1. The positive input of each comparator monitors the voltage on the IS+ pins referenced to VSSS. One comparator has an integrated reference, VREF+, at the comparator negative input terminal. The second comparator has an integrated reference, VREF-, at the comparator negative input terminal. Both references have an overall accuracy of ±1.5% over voltage and temperature. The reference voltages are not available externally.

Figure 6-1 Comparator Block Diagram

The outputs of the comparators, R_CMP and S_CMP, interface to logic that controls the state of VDRV based on the output state of each comparator as shown in VDRV Control Logic

Figure 6-2 VDRV Control Logic