To achieve optimal electrical and thermal performance, an optimized PCB layout is required. GUID-4099970F-40F4-46B0-AE66-3E56BEF936C1.html#SLVSA437079 through GUID-4099970F-40F4-46B0-AE66-3E56BEF936C1.html#SLVSAW7_GNDLAYER shows a typical PCB layout. Some considerations for an optimized layout are:

• Use large copper areas for power planes (PVIN, VOUT, and PGND) to minimize conduction loss and thermal stress.
• Place ceramic input and output capacitors close to the device pins to minimize high frequency noise.
• Locate additional output capacitors between the ceramic capacitor and the load.
• Keep AGND and PGND separate from one another. The connection is made internal to the device.
• Place R_VSEL, R_ADJ, R_RT, R_MODE, and C_SS as close as possible to their respective pins.
• Use multiple vias to connect the power planes (PVIN, VOUT, and PGND) to internal layers.