ZHCSLW0A September   2020  – December 2020 TPSM41625

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics (PVIN = 12 V)
    7. 6.7 Typical Characteristics (PVIN = 5 V)
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Setting the Output Voltage
      2. 7.3.2  Output Voltage Current Rating
      3. 7.3.3  RS+/RS- Remote Sense Function
      4. 7.3.4  Ramp Select (RAMP and RAMP_SEL)
      5. 7.3.5  Switching Frequency (RT)
      6. 7.3.6  Synchronization (SYNC)
        1. 7.3.6.1 Loss of Synchronization
      7. 7.3.7  Stand-alone/Stackable Operation
        1. 7.3.7.1 Stackable Synchronization
          1. 7.3.7.1.1 Sync Configuration
          2. 7.3.7.1.2 Clock Sync Point Selection
          3. 7.3.7.1.3 Configuration 1: Dual Phase, Primary Sync-Out Clock to Secondary
          4. 7.3.7.1.4 Configuration 2: Dual Phase, Primary and Secondary Sync to External System Clock
      8. 7.3.8  Improved Transient Performance versus Fixed Frequency (Stand-alone Operation Only)
      9. 7.3.9  Output On/Off Enable (EN)
      10. 7.3.10 Power Good (PGOOD)
      11. 7.3.11 Soft-Start Operation
      12. 7.3.12 Input Capacitor Selection
      13. 7.3.13 Output Capacitor Selection
      14. 7.3.14 Current Limit (ILIM)
      15. 7.3.15 Safe Start-up into Pre-Biased Outputs
      16. 7.3.16 Overcurrent Protection
      17. 7.3.17 Output Overvoltage and Undervoltage Protection
      18. 7.3.18 Overtemperature Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active Mode
      2. 7.4.2 Shutdown Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Output Voltage Setpoint
        3. 8.2.2.3 Setting the Switching Frequency
        4. 8.2.2.4 RAMP Setting
        5. 8.2.2.5 Input Capacitors
        6. 8.2.2.6 Output Capacitors
      3. 8.2.3 Application Waveforms
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
      1. 10.2.1 Package Specifications
      2. 10.2.2 EMI
        1. 10.2.2.1 EMI Plots
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Custom Design With WEBENCH® Tools
    2. 11.2 接收文档更新通知
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 静电放电警告
    6. 11.6 术语表
  12. 12Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

GUID-E29C08C2-4B43-4000-AFD3-28D6F06140A8-low.gif Figure 5-1 69-Pin QFN MOV Package (Top View)
Table 5-1 Pin Functions
PIN TYPE (1) DESCRIPTION
NAME NO.
AGND 19 G Analog ground. Zero voltage reference for internal references and logic. Do not connect this pin to PGND; the connection is made internal to the device.
BP5 21, 22 O Output of an internal 5-V regulator used for the controller driver stage within the module. This output can be used to connect a pullup resistor to the PGOOD pin. Leave these pins open if not used as a pullup for PGOOD.
DNC 38, 40 – Do Not Connect. Do not connect these pins to AGND, PGND, another DNC pin, or any other voltage. These pins are connected to internal circuitry. Each pin must be soldered to an isolated pad.
EN 25 I Enable pin. This pin turns the converter on when floated or opened. This pin is internally pulled up to the BP5 voltage when left open. The converter can be turned off by either driving it directly with a logic input or an open drain/collector device to connect this pin to AGND. An external voltage divider can be placed between this pin, AGND, and PVIN/VIN to create an external UVLO.
ILIM 20 I Current limit setting pin. This pin sets the current limit threshold of the converter. Leave this pin open for the full current limit threshold. The current limit threshold can be lowered by connecting an appropriate resistor from this pin to AGND.
ISHARE 23 O Current sharing pin. This pin is interconnected between modules for multi-phase configurations. Leave this pin open for single-phase configurations.
MODE 31 I Mode select pin. This pin is used to configure the module for single-phase or multi-phase operation. For single-phase operation, this pin is used to select the API and Body Brake functions. For multi-phase operation, this pin selects the primary/secondary and SYNC configurations.
NC 39, 41, 45-52 – Not connected. These pins are not connected to any circuitry within the module. It is recommended that these pins be connected to the PGND plane on the application board to enhance shielding and thermal performance.
PGND 8-11, 17, 18, 34, 37, 53-58, 68 G This is the return path for the power stage of the device. Connect these pins to the input supply return, load return, and bypass capacitors associated with the PVIN and VOUT pins.
PGOOD 26 O Power Good pin. Open-drain output that asserts low if the remote sense feedback voltage is not within the specified PGOOD thresholds. When using this signal as an output, a pullup resistor is required. If unused, leave this pin open. The BP5 output can be used as the pullup voltage source.
PVIN 12-15, 67 I Input switching voltage. Supplies voltage to the power switches of the converter. Connect these pins to the input supply. Connect bypass capacitors between these pins and PGND, close to the module.
RAMP 32 I Internal ramp selection. This pin is used to select an internal ramp amplitude. See Table 7-3 for recommended settings. An internal 78.7-kΩ resistor is connected between RAMP and RAMP_SEL within the module. To select the internal resistor, it is recommended to leave this pin open and to connect the RAMP_SEL pin to AGND.
RAMP_SEL 33 I Internal default ramp selection. This pin is used to select the internal default ramp selection for the control loop. An internal 78.7-kΩ resistor is connected between RAMP and RAMP_SEL pins. Connect the RAMP_SEL pin to AGND and leave the RAMP pin open to select the internal resistor.
RS+ 35 I Positive input to the internal differential remote sense amplifier. This pin is used for the feedback connection to VOUT. Connect this pin to the output voltage at the load. This connection can be made using a direct connection or an external upper feedback resistor, depending on the magnitude of VOUT and the VSEL selection. A 1-kΩ lower feedback resistor is connected across RS+ and RS– internal to the module. The RS+ connection is not needed for secondary devices in multi-phase configurations, and should be left open.
RS– 36 I Negative input to the internal differential remote sense amplifier. This pin is used for the feedback connection to VOUT return. Connect this pin to the output voltage return at the load. A 1-kΩ lower feedback resistor is connected across RS+ and RS– internal to the module. The RS- connection is not needed for secondary devices in multi-phase configurations, and should be left open.
RT 30 I Switching frequency setting pin. This analog pin is used to set the switching frequency of the converter by placing an external resistor from this pin to AGND. This pin also selects the phase interleaving of the module when used in multi-phase configurations.
SS 29 I Soft-start selection pin. This pin is used to select the soft-start time. Ten possible selections are available by connecting an appropriate resistor from this pin to AGND. The selections range from 0.5 ms to 32 ms.
SW 42-44 O Switch node. These pins are connected to the internal output inductor and switching MOSFETs. Connect these pins together using a small copper island beneath the device. Keep this copper island to a minimum to prevent issues with noise and EMI.
SYNC 27 I Frequency synchronization pin. MODE can be used to configure this pin as a sync input or a sync output for external clock and multi-phase primary/secondary configurations.
VIN 16 I Input bias voltage. Supplies the control circuitry of the power converter. Connect a 1-µF bypass capacitor from this pin to PGND (pins 17 and 18) in close proximity to the module. For split rail applications, connect this pin to an input bias supply. For strapped rail applications, connect this pin to PVIN through a 0 Ω to 10 Ω resistor.
VOUT 1-7, 59-66, 69 O Output voltage. These pins are connected to the internal output inductor. Connect these pins to the output load and connect external bypass capacitors between these pins and PGND in close proximity to the module.
VSEL 28 I Internal reference voltage selection. This pin is used to select the desired internal reference voltage. Ten possible selections are available by connecting an appropriate resistor from this pin to AGND. The selections range from 0.6 V to 1.1 V.
VSHARE 24 O Voltage sharing pin. This pin is interconnected between modules for multi-phase configurations. Leave this pin open for single-phase configurations.
(1) G = Ground, I = Input, O = Output, – = Not Connected
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