To achieve optimal electrical and thermal performance, an optimized PCB layout is required. Figure 10-1 through Figure 10-3 shows a typical PCB layout. The following are some considerations for an optimized layout.

• Use large copper areas for power planes (VIN, VOUT, and PGND) to minimize conduction loss and thermal stress.
• Place ceramic input and output capacitors close to the device pins to minimize high frequency noise.
• Locate additional output capacitors between the ceramic capacitor and the load.
• Connect AGND to PGND at a single point.
• Place R_FBT and R_FBB as close as possible to the FB pin.
• Use multiple vias to connect the power planes to internal layers.
• Download the EVM Design Files for fast board design