To achieve optimal electrical and thermal performance, an optimized PCB layout is required. Figure 11-1 and Figure 11-2 show a typical PCB layout. Some considerations for an optimized layout are:

• Use large copper areas for power planes (VIN, VOUT, and PGND) to minimize conduction loss and thermal stress.
• Connect all PGND pins together using copper plane.
• Connect AGND pin to the PGND copper at a single point near the pin.
• Place ceramic input and output capacitors close to the device pins to minimize high frequency noise.
• Locate additional output capacitors between the ceramic capacitor and the load.
• Place R_FBT and R_FBB as close as possible to their respective pins.
• Use multiple vias to connect the power planes to internal layers.