For protection against load faults, the TPSM5D1806E implements a cycle-by-cycle peak current protection. When the inductor current hits the peak current limit threshold, the high-side FET turns off and the low-side FET turns on. The device monitors the valley current threshold during the high-side FET off time. If the inductor current clears the valley current threshold, the high-side FET will turn on at the next clock edge. However, if the inductor current remains higher than the valley current threshold, the next high-side FET cycle is skipped, the low-side FET remains on, and an internal counter is incremented. This counter increments every clock edge as long as the inductor current remains higher than the valley current threshold. If the current falls below the valley current threshold at the next clock edge, the counter is reset. If the counter increments 16 consecutive clock cycles, a current limit fault is identified and the device enters hiccup mode to reduce power dissipation. In hiccup mode, the module continues in a cycle of successive shutdown and power up until the load fault is removed. During this period, the average current flowing into the fault is significantly reduced, which reduces power dissipation. Once the fault is removed, the module automatically recovers and returns to normal operation.