10.1 Layout Guidelines

A recommended PCB layout for the TPSM82480 dual phase solution is shown below. It ensures best electrical and optimized thermal performance considering the following important topics:

- Both V_OUT1 and V_OUT2 must be connected to build a common VOUT structure.

- The input capacitors must be placed as close as possible to the appropriate pins of the device. This provides low resistive and inductive paths for the high di/dt input current. The input capacitance is split, as is the V_IN connection, to avoid interference between the input lines.

- The V_OUT regulation loop is closed with C_OUT and its ground connection. To avoid PGND noise crosstalk, PGND is kept split for the regulation loop. If a ground layer or plane is used, a direct connection by vias, as shown, is recommended. Otherwise the connection of C_OUT to GND must be short for good load regulation.

- The FB node is sensitive to dv/dt signals. Therefore the resistive divider should be placed close to the FB (and RS pin in case of using R₃) pin, avoiding long trace distance.

For more detailed information about the actual EVM solution, see SLVUAI6.

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