米6体育平台手机版

ZHCSPT6D July 2023 – June 2024 TPSM8287A06 , TPSM8287A10 , TPSM8287A12 , TPSM8287A15

PRODUCTION DATA

封装选项

机械数据 (封装 | 引脚)

RDW|39
- MPQF792A

散热焊盘机械数据 (封装 | 引脚)

订购信息

9.3.2.1 Selecting the Input Capacitors

The TPSM8287Axx devices feature a butterfly or parallel layout with two pairs of VIN and GND pins on opposite sides of the package.

The duty cycle of the converter is given by:

Equation 40.

D = \frac{V_{O U T}}{η {\times V}_{I N}}

Equation 41.

D = \frac{0.60}{0.78 \times 2.7} = 0.284

The value of input capacitance needed to meet any system-level input voltage ripple requirement is given by Equation 42. For this example, the lowest input voltage and highest load current are used to generate a worst case input voltage ripple of 100 mV.

Equation 42.

C_{I N} = \frac{D \times (1 - D) \times I_{O U T}}{V_{I N (P P)} {\times f}_{s w}}

Equation 43.

C_{I N} = \frac{0.284 \times (1 - 0.284) \times 12.0}{0.1 \times 1.5 \times 10^{6}} = 16.3 μ F

The value of C_IN calculated with Equation 42 is the effective capacitance after all derating, tolerance, and aging effects have been considered. In this parallel configuration it is important to distribute the calculated input capacitance equally accross all phases.