A high level on the MODE/SYNC pin selects forced-PWM operation. A low level on the MODE/SYNC pin selects power-save operation, in which the device automatically transitions between PWM and PFM according to the load conditions.

If applying a valid clock signal to the MODE/SYNC pin, the device synchronizes the switching cycles to the external clock and automatically selects forced-PWM operation. When applying a frequency modulated clock to the MODE/SYNC pin, the device also follows this. This action can be useful in applications where the converter must follow an external Spread Spectrum Modulation.

The MODE/SYNC pin is logically ORed with the FPWMEN bit in the CONTROL1 register. Setting either high enables FPWM (see Section 7.3.2).

When multiple devices are used in a stacked / parallel configuration to increase the output current, the clock signal from the primary device must cascade through all devices in a daisy chain configuration. The SYNC_OUT pin of the previous device must connect to the MODE/SYNC pin of the next device in the chain (see Section 7.3.17).