ZHCSR76 November 2022 TPSM82901
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
SUPPLY | ||||||
IQ_PSM | Operating Quiescent Current (Power Save Mode) | Iout = 0 mA, device not switching | 4 | µA | ||
IQ_PWM | Operating Quiescent Current (PWM Mode) | VIN=12 V, VOUT=1.2 V; Iout = 0 mA, device switching | 8 | mA | ||
ISD | Shutdown current into VIN pin | EN = 0 V | 0.27 | 3.5 | µA | |
VUVLO | Under Voltage Lock-Out | VIN rising | 2.85 | 2.925 | 3.0 | V |
Under Voltage Lock-Out | VIN falling | 2.7 | 2.775 | 2.85 | V | |
VUVLO_HYS | Under Voltage Lock-Out Hysteresis | Hysteresis | 150 | mV | ||
CONTROL & INTERFACE | ||||||
ILKG | EN Input leakage current | EN = 12 V | 10 | 300 | nA | |
VIH_MODE | High-Level Input Voltage at MODE/S-CONF-Pin | 1.0 | V | |||
TSD | Thermal Shutdown Threshold | TJ rising | 170 | °C | ||
Thermal Shutdown Hysteresis | Hysteresis | 20 | ||||
VIH | High-level input voltage at EN-Pin | 0.97 | 1.0 | 1.03 | V | |
VIL | Low-level input voltage at EN-Pin | 0.87 | 0.9 | 0.93 | V | |
REN_PD | Smart-Enable Internal Pulldown Resistor | EN = LOW | 0.5 | MΩ | ||
VPG | Power good threshold | VFB rising, referenced to VFB nominal | 93.5% | 96% | 99% | |
VFB falling, referenced to VFB nominal | 88.5% | 93% | 96% | |||
Hysteresis | 1.5% | 3.5% | 6% | |||
VPG_OL | Low-level output voltage at PG pin | ISINK = 1 mA | 0.4 | V | ||
IPG_LKG | Input leakage current into PG pin | VPG = 5 V | 15 | 550 | nA | |
tPG_DLY | Power good delay time | VFB falling | 32 | µs | ||
RSET | S-CONF/VSET Resistor Tolerance | –4 | +4 | % | ||
CSET | Maximum Capacitance connected to S-CONF/VSET Pins | 30 | pF | |||
POWER SWITCHES | ||||||
ILKG_SW | Leakage current into SW-Pin | VSW = VOS = 5.5 V | 2 | 7 | µA | |
RDS_ON | High-side FET on resistance | VIN > 4 V, ISW = 500 mA | 62 | 111 | mΩ | |
Low-side FET on resistance | VIN > 4 V, ISW = 500 mA | 22 | 40 | |||
ILIM | High-side FET current limit | TPSM82901 | 2.6 | 3.4 | 4.3 | A |
Low-side FET current limit | TPSM82901 | 2.4 | 2.8 | 3.2 | A | |
ILIM_SINK | Low-side FET sink current limit | 1.3 | 1.7 | 2.5 | A | |
fSW | Switching frequency | 2.5-MHz selection | 2.5 | MHz | ||
TON(MIN) | Minimum On-time | 50 | ns | |||
fSW | Switching frequency | 1.0-MHz selection | 1.0 | MHz | ||
D | Dutycycle | 1 | ||||
RPD | Dropout resistance | 100% mode, VIN > 4 V | 100 | mΩ | ||
OUTPUT | ||||||
VO_Reg1 | Output Voltage Regulation | VSET Configuration selected. TJ = 25°C. | –0.9% | +0.9% | ||
VO_Reg2 | Output Voltage Regulation | VSET Configuration selected. 0 °C< TJ < 85°C | –1.1% | +1.1% | ||
VO_Reg3 | Output Voltage Regulation | VSET Configuration selected. –40°C < TJ < 125°C | –1.25% | +1.25% | ||
VFB | Feedback Regulation Voltage | Adjustable Configuration selected | 0.6 | V | ||
VFB_Reg1 | Feedback Voltage Regulation | FB-Option selected. TJ = 25°C. | –0.6% | +0.6% | ||
VFB_Reg2 | Feedback Voltage Regulation | FB-Option selected. 0°C < TJ < 85°C. | –0.65% | +0.65% | ||
VFB_Reg3 | Feedback Voltage Regulation | FB-Option selected. –40°C < TJ < 125°C | –0.9% | +0.9% | ||
IFB | Input leakage current into FB pin | Adjustable configuration, VFB = 0.6 V | 1 | 70 | nA | |
Tdelay | Start-up delay time | IO = 0 mA, time from EN=HIGH until start switching, Adjustable Configuration selected | 600 | 1400 | µs | |
Start-up delay time | IO = 0 mA, time from EN=HIGH until start switching, VSET Configuration selected. The typical value is based on the first option of VSET configuration. | 650 | 1850 | µs | ||
TSS | Soft-Start time | IO = 0 mA after Tdelay, from 1st switching pulse until target VO; TR/SS-Pin = OPEN | 150 | 200 | µs | |
ISS | SS/TR source current | 2.3 | 2.5 | 2.7 | µA | |
VFB/VSS/TR | Tracking Gain, Adjustable Configuration | 0.75 | ||||
VFB/VSS/TR | Tracking Gain tolerance | ±8 | mV | |||
RDISCH | Active Discharge Resistance | Discharge = ON - Option Selected, EN = LOW, | 7.5 | 20 | Ω |