ZHCSR75 November 2022 TPSM82902
PRODUCTION DATA
- 1 特性
- 2 应用
- 3 说明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Mode Selection and Device Configuration (MODE/S-CONF)
- 7.3.2 Adjustable VO Operation (External Voltage Divider)
- 7.3.3 Setable VO Operation (VSET and Internal Voltage Divider)
- 7.3.4 Soft Start/Tracking (SS/TR)
- 7.3.5 Smart Enable with Precise Threshold
- 7.3.6 Power Good (PG)
- 7.3.7 Undervoltage Lockout (UVLO)
- 7.3.8 Current Limit And Short Circuit Protection
- 7.3.9 Thermal Shutdown
- 7.4 Device Functional Modes
- 8 Application and Implementation
- 9 Device and Documentation Support
- 10Mechanical, Packaging, and Orderable Information
7.4.4 100% Duty-Cycle Operation
The duty cycle of the buck converter operating in PWM mode is given as D = VOUT/VIN. The duty cycle increases as the input voltage comes close to the output voltage and the off time gets smaller. When the minimum off time of typically 80 ns is reached, the TPSM82902 scales down its switching frequency while it approaches 100% mode. In 100% mode, the device keeps the high-side switch on continuously. The high-side switch stays turned on as long as the output voltage is below the internal set point. This allows the conversion of small input to output voltage differences (for example, getting longest operation time of battery-powered applications). In 100% duty cycle mode, the low-side FET is switched off.
The minimum input voltage to maintain output voltage regulation, depending on the load current and the output voltage level, can be calculated as:
where
- IOUT is the output current.
- RDS(on) is the on-state resistance of the high-side FET.
- RL is the DC resistance of the inductor used (approximately 40 mΩ).