米6体育平台手机版

ZHCSOW9C october 2022 – july 2023 TPSM82912 , TPSM82913 , TPSM82913E

PRODUCTION DATA

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机械数据 (封装 | 引脚)

RDU|28
- MPQF678

散热焊盘机械数据 (封装 | 引脚)

订购信息

6.5 Electrical Characteristics

Over recommended input voltage range, T_J= -40 ℃ to 125 ℃, (T_J= -55 ℃ to 125 ℃ for -ET parts). Typical values are at Vin = 12 V andT_J= 25 ℃ (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SUPPLY
I_Q	Quiescent current	EN = High, no load, device switching, fsw = 1 MHz		5		mA
I_SD	Shutdown current	EN = GND		0.3	70	µA
V_UVLO	Under voltage lockout	V_IN rising	2.85	2.92	3.0	V
V_UVLO	Under voltage lockout	V_IN rising			3.04	V
V_HYS	Under voltage lockout hysteresis			200		mV
T_JSD	Thermal shutdown threshold	T_J rising		170		°C
T_JSD	Thermal shutdown hysteresis	T_J falling		20		°C
CONTROL and INTERFACE
V_{H_EN}	High-level input-threshold voltage at EN/SYNC		0.97	1.01	1.04	V
V_{L_EN}	Low-level input-threshold voltage at EN/SYNC		0.87	0.9	0.93	V
V_{H_SYNC}	High-level input-threshold clock signal on EN/SYNC	EN/SYNC = clock	1.1			V
V_{L_SYNC}	Low-level input-threshold clock signal on EN/SYNC	EN/SYNC = clock			0.4	V
I_EN,LKG	Input leakage current into EN/SYNC	EN/SYNC = GND or VIN		5	160	nA
R_PD	Pull-down resistor on EN/SYNC	EN/SYNC = Low	330	500		kΩ
t_delay	Enable delay time	Time from EN/SYNC high to device starts switching, R_S-CONF = 80.6 kΩ		1		ms
I_NR/SS	NR/SS source current		67.5	75	82.5	µA
R_S-CONF	S-CONF resistor step range accuracy	R_S-CONF tolerance for all settings according to Table 7-1	-4		+4	%
C_S-CONF	Maximum capacitance connected to S-CONF pin				30	pF
V_PG	Power good threshold	V_FB rising, referenced to V_FB nominal	93	95	98	%
V_PG	Power good threshold	V_FB falling, referenced to V_FB nominal	88	90	93	%
V_PG,OL	Low-level output voltage at PG pin	I_SINK = 1 mA			0.4	V
I_PG,LKG	Input leakage current into PG pin	V_PG = 5 V		5	500	nA
t_PG,DLY	Power good delay time	V_FB falling		8		µs
OUTPUT
t_on	Minimum on-time	V_IN ≥ 5 V, I_out= 1 A		35	70	ns
t_off	Minimum off-time	V_IN ≥ 5 V, I_out= 1 A		50	60	ns
V_FB	Feedback regulation accuracy	–40℃ ≤ T_J ≤ 125℃	0.792	0.8	0.808	V
I_FB,LKG	Input leakage current into FB	V_FB = 0.8 V		1	70	nA
PSRR	Power supply rejection ratio	V_IN= 12 V, 1.2 V_OUT, 1 A, C_NR/SS= 220 nF, f_sw= 1 MHz, C_FF= open, C_OUT = 3 x 22 µF, f ≤ 100 kHz		65		dB
V_NRMS	Output voltage RMS noise	V_IN= 12 V, BW = 100 Hz to 100 kHz, C_NR/SS= 220 nF, f_SW= 1 MHz, V_OUT= 1.2 V, C_FF= open, C_OUT = 3 x 22 µF		27.4		µV_RMS
V_NRMS	Output voltage RMS noise	V_IN= 5 V, BW = 100 Hz to 100 kHz, C_NR/SS= 220 nF, f_SW= 2.2 MHz, V_OUT= 1.2 V, C_FF= open, C_OUT = 3 x 22 µF		13.3		µV_RMS
V_opp	Output ripple voltage at f_SW	V_IN= 12 V, f_SW= 1 MHz, V_OUT= 1.2 V, C_OUT = 3 x 22 µF, L_f= 10 nH, C_f= 2 x 22 µF		9		µV_RMS
V_opp	Output ripple voltage at f_SW	V_IN= 5 V, f_SW= 2.2 MHz, V_OUT= 1.2V, C_OUT = 3 x 22 µF, L_f= 10 nH, C_f= 2 x 22 uF		< 3		µV_RMS
R_DIS	Output discharge resistance	EN/SYNC = GND, V_OUT= 1.2 V, V_IN ≥ 5 V. See Section 6.6 for plot.		7		Ω
R_DIS	Output discharge resistance	EN/SYNC = GND, V_OUT= 5 V, V_IN ≥ 5 V. See Section 6.6 for plot.		32		Ω
f_SW	Switching frequency	2.2-MHz setting	1.98	2.2	2.42	MHz
f_SW	Synchronization range	2.2-MHz setting	1.9	2.2	2.42	MHz
f_SW	Switching frequency	1-MHz setting	0.9	1	1.18	MHz
f_SW	Synchronization range	1-MHz setting	0.86	1	1.2	MHz
D_SYNC	Synchronization duty cycle		45		55	%
t_{sync_delay}	Synchronization phase delay	Phase delay from EN/SYNC rising edge to SW rising edge		90		ns
I_SWpeak	Peak switch current limit	TPSM82912⁽¹⁾	2.9	3.5	4.0	A
I_SWpeak	Peak switch current limit	TPSM82913	3.7	4.3	5.1	A
I_SWvalley	Valley switch current limit	TPSM82912⁽¹⁾		3.4		A
I_SWvalley	Valley switch current limit	TPSM82913		4.2		A
Ineg_valley	Negative valley current limit			-1.39	-0.96	A
R_DS(ON)	High-side FET on-resistance	V_IN ≥ 5 V		57	95	mΩ
R_DS(ON)	Low-side FET on-resistance	V_IN ≥ 5 V		20	39	mΩ

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