ZHCSIO9A August   2018  – June 2021 TPSM831D31

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  References: DAC
    7. 6.7  Telemetry
    8. 6.8  Current Sense and Calibration
    9. 6.9  Logic Interface Pins: A_EN, A_PGOOD, B_EN, B_PGOOD,RESET
    10. 6.10 Protections: OVP and UVP
    11. 6.11 Typical Characteristics (VIN = 12 V)
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 DCAP+ Control
      2. 7.3.2 Setting the Load-Line (DROOP)
      3. 7.3.3 Start-Up Timing
      4. 7.3.4 Load Transitions
      5. 7.3.5 Switching Frequency
      6. 7.3.6 RESET Function
      7. 7.3.7 VID Table
    4. 7.4 Device Functional Modes
      1. 7.4.1 Continuous Conduction Mode
      2. 7.4.2 Operation With EN Signal Control
      3. 7.4.3 Operation With OPERATION Control
      4. 7.4.4 Operation With EN and OPERATION Control
    5. 7.5 Programming
      1. 7.5.1  PMBus Connections
      2. 7.5.2  PMBus Address Selection
      3. 7.5.3  Supported Commands
      4. 7.5.4  Commonly Used PMBus Commands
      5. 7.5.5  Voltage, Current, Power, and Temperature Readings
        1. 7.5.5.1 (88h) READ_VIN
        2. 7.5.5.2 (89h) READ_IIN
        3. 7.5.5.3 (8Bh) READ_VOUT
        4. 7.5.5.4 (8Ch) READ_IOUT
        5. 7.5.5.5 (8Dh) READ_TEMPERATURE_1
        6. 7.5.5.6 (96h) READ_POUT
        7. 7.5.5.7 (97h) READ_PIN
        8. 7.5.5.8 (D4h) MFR_SPECIFIC_04
      6. 7.5.6  Output Current Sense and Calibration
        1. 7.5.6.1 Reading Individual Phase Currents
          1. 7.5.6.1.1 Reading Total Current
          2. 7.5.6.1.2 51
      7. 7.5.7  Output Voltage Margin Testing
        1. 7.5.7.1 (01h) OPERATION
        2. 7.5.7.2 (26h) VOUT_MARGIN_LOW
        3. 7.5.7.3 (25h) VOUT_MARGIN_HIGH
      8. 7.5.8  Loop Compensation
        1. 7.5.8.1 (D7h) MFR_SPECIFIC_07
        2. 7.5.8.2 (28h) VOUT_DROOP
      9. 7.5.9  Converter Protection and Response
      10. 7.5.10 Output Overvoltage Protection and Response
        1. 7.5.10.1 (40h) VOUT_OV_FAULT_LIMIT
        2. 7.5.10.2 (41h) VOUT_OV_FAULT_RESPONSE
      11. 7.5.11 Maximum Allowed Output Voltage Setting
        1. 7.5.11.1 (24h) VOUT_MAX
      12. 7.5.12 Output Undervoltage Protection and Response
        1. 7.5.12.1 (44h) VOUT_UV_FAULT_LIMIT
        2. 7.5.12.2 (45h) VOUT_UV_FAULT_RESPONSE
      13. 7.5.13 Minimum Allowed Output Voltage Setting
        1. 7.5.13.1 (2Bh) VOUT_MIN
      14. 7.5.14 Output Overcurrent Protection and Response
        1. 7.5.14.1 (46h) IOUT_OC_FAULT_LIMIT
        2. 7.5.14.2 (4Ah) IOUT_OC_WARN_LIMIT
        3. 7.5.14.3 (47h) IOUT_OC_FAULT_RESPONSE
        4. 7.5.14.4 Per Phase Overcurrent Limit Thresholds
      15. 7.5.15 Input Under-Voltage Lockout (UVLO)
        1. 7.5.15.1 (35h) VIN_ON
      16. 7.5.16 Input Over-Voltage Protection and Response
        1. 7.5.16.1 (55h) VIN_OV_FAULT_LIMIT
        2. 7.5.16.2 (56h) VIN_OV_FAULT_RESPONSE
      17. 7.5.17 Input Undervoltage Protection and Response
        1. 7.5.17.1 (59h) VIN_UV_FAULT_LIMIT
        2. 7.5.17.2 (5Ah) VIN_UV_FAULT_RESPONSE
      18. 7.5.18 Input Overcurrent Protection and Response
        1. 7.5.18.1 (5Bh) IIN_OC_FAULT_LIMIT
        2. 7.5.18.2 (5Dh) IIN_OC_WARN_LIMIT
        3. 7.5.18.3 (5Ch) IIN_OC_FAULT_RESPONSE
      19. 7.5.19 Overtemperature Protection and Response
        1. 7.5.19.1 (4Fh) OT_FAULT_LIMIT
        2. 7.5.19.2 (51h) OT_WARN_LIMIT
        3. 7.5.19.3 (50h) OT_FAULT_RESPONSE
      20. 7.5.20 Dynamic Phase Shedding (DPS)
        1. 7.5.20.1 (DEh) MFR_SPECIFIC_14
        2. 7.5.20.2 (DFh) MFR_SPECIFIC_15
      21. 7.5.21 NVM Programming
      22. 7.5.22 NVM Security
        1. 7.5.22.1 (FAh) MFR_SPECIFIC_42
      23. 7.5.23 Black Box Recording
        1. 7.5.23.1 (D8h) MFR_SPECIFIC_08
      24. 7.5.24 Board Identification and Inventory Tracking
      25. 7.5.25 Status Reporting
        1. 7.5.25.1 (78h) STATUS_BYTE
        2. 7.5.25.2 (79h) STATUS_WORD
        3. 7.5.25.3 (7Ah) STATUS_VOUT
        4. 7.5.25.4 (7Bh) STATUS_IOUT
        5. 7.5.25.5 (7Ch) STATUS_INPUT
        6. 7.5.25.6 (7Dh) STATUS_TEMPERATURE
        7. 7.5.25.7 (7Eh) STATUS_CML
        8. 7.5.25.8 (80h) STATUS_MFR_SPECIFIC
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Capacitors
        2. 8.2.2.2 Output Capacitors
        3. 8.2.2.3 Switching Frequency
        4. 8.2.2.4 Set PMBus Address
        5. 8.2.2.5 PMBus GUI Default Values
      3. 8.2.3 Application Performance Plots
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 接收文档更新通知
    2. 11.2 支持资源
    3. 11.3 Trademarks
    4. 11.4 静电放电警告
    5. 11.5 术语表
  12. 12Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
  • MOA|28
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.5.8 Loop Compensation

The TPSM831D31 provides several options for tuning the output voltage feedback and response to transients. These may be configured by programming the MFR_SPECIFIC_07, VOUT_DROOP, and MFR_SPECIFIC_14. Several such parameters may be configured through these commands:

  • DC Load Line - Selects the DC shift in output voltage corresponding to increased output current. The DC load line affects both the final value the output voltage settles to, as well as the settling time. Use the VOUT_DROOP command to select the DC load line.
  • Integration Time Constant - In order to maintain DC accuracy, the control loop includes an integration stage. Use MFR_SPECIFIC_07 to select the integration time constant.
  • Integration Path Gain - The gain of the integration and AC paths may be selected independently. The AC and DC gains both affect the small-signal bandwidth of the converter. Use MFR_SPECIFIC_07 to select the integration path gain.
  • AC Load Line - Selects the AC response to output voltage error. The AC load line affects the settling and response time following a load transient event. MFR_SPECIFIC_07 Use the MFR_SPECIFIC_07 command to select the AC load line.
  • AC Path Gain - The gain of the integration and AC paths may be selected independently. The AC and DC gains both affect the small-signal bandwidth of the converter. Use MFR_SPECIFIC_07 to select the AC path gain.
  • Ramp Amplitude - Smaller ramp settings result in faster response, but may also lead to increased frequency jitter. Likewise, large ramp settings result in lower frequency jitter, but may be slightly slower to respond to changing conditions. The ramp setting also affects the small-signal bandwidth of the converter. Use MFR_SPECIFIC_14 to select the ramp high setting.
Table 7-19 Dynamic Integration and Undershoot Reduction (TA = 25°C)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VDYN Dynamic integration voltage setting MFR_SPEC_12<10:8> = 000b; 90 100 116 mV
MFR_SPEC_12<10:8> = 001b; 135 150 175 mV
MFR_SPEC_12<10:8> = 010b; 175 200 230 mV
MFR_SPEC_12<10:8> = 011b; 225 250 285 mV
MFR_SPEC_12<10:8> = 100b; 270 300 345 mV
MFR_SPEC_12<10:8> = 101b; 315 350 400 mV
MFR_SPEC_12<10:8> = 110b; 360 400 455 mV
MFR_SPEC_12<10:8> = 111b; OFF mV
tDINT Dynamic integration time constant MFR_SPEC_12<7:4> = 0000b; 1 µs
MFR_SPEC_12<7:4> = 0001b; 2 µs
MFR_SPEC_12<7:4> = 0010b; 3 µs
MFR_SPEC_12<7:4> = 0011b; 4 µs
MFR_SPEC_12<7:4> = 0100b; 5 µs
MFR_SPEC_12<7:4> = 0101b; 6 µs
MFR_SPEC_12<7:4> = 0110b; 7 µs
MFR_SPEC_12<7:4> = 0111b; 8 µs
MFR_SPEC_12<7:4> = 1000b; 12 µs
MFR_SPEC_12<7:4> = 1001b; 13 µs
MFR_SPEC_12<7:4> = 1010b; 14 µs
MFR_SPEC_12<7:4> = 1011b; 15 µs
MFR_SPEC_12<7:4> = 1100b; 16 µs
MFR_SPEC_12<7:4> = 1101b; 17 µs
MFR_SPEC_12<7:4> = 1110b; 18 µs
MFR_SPEC_12<7:4> = 1111b; 19 µs
VUSR2 USR level 2 voltage setting MFR_SPEC_09<14:12> = 000b; 120 140 160 mV
MFR_SPEC_09<14:12> = 001b; 155 180 205 mV
MFR_SPEC_09<14:12> = 010b; 190 220 245 mV
MFR_SPEC_09<14:12> = 011b; 230 260 290 mV
MFR_SPEC_09<14:12> = 100b; 265 300 335 mV
MFR_SPEC_09<14:12> = 101b; 300 340 375 mV
MFR_SPEC_09<14:12> = 110b; 335 380 420 mV
MFR_SPEC_09<14:12> = 111b; OFF mV
VUSR1 USR level 1 voltage setting MFR_SPEC_09<2:0> = 000b; 70 90 110 mV
MFR_SPEC_09<2:0> = 001b; 100 120 140 mV
MFR_SPEC_09<2:0> = 010b; 130 150 170 mV
MFR_SPEC_09<2:0> = 011b; 160 180 205 mV
MFR_SPEC_09<2:0> = 100b; 185 210 240 mV
MFR_SPEC_09<2:0> = 101b; 215 240 270 mV
MFR_SPEC_09<2:0> = 110b; 240 270 305 mV
MFR_SPEC_09<2:0> = 111b; OFF mV
PHUSR1 Maximum phase added in USR level 1 MFR_SPEC_09<5> = 0b; 3 phases
MFR_SPEC_09<5> = 1b; 4 phases
VOUSRHYS Dynamic integration/USR voltage hysteresis MFR_SPEC_09<4:3> = 00b; 2 5 9 mV
MFR_SPEC_09<4:3> = 01b; 5 10 15 mV
MFR_SPEC_09<4:3> = 10b; 10 15 20 mV
MFR_SPEC_09<4:3> = 11b; 15 20 25 mV
Table 7-20 Ramp Selections
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VRAMP RAMP Setting MFR_SPEC_14<2:0> = 000b 30 40 55 mV
MFR_SPEC_14<2:0> = 001b 70 80 95 mV
MFR_SPEC_14<2:0> = 010b 110 120 135 mV
MFR_SPEC_14<2:0> = 011b 150 160 175 mV
MFR_SPEC_14<2:0> = 100b 190 200 215 mV
MFR_SPEC_14<2:0> = 101b 230 240 255 mV
MFR_SPEC_14<2:0> = 110b 270 280 300 mV
MFR_SPEC_14<2:0> = 111b 305 320 335 mV
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