ZHCSIO9A August 2018 – June 2021 TPSM831D31
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
RRPGDL | Open-drain pulldown resistance | VA_PGOOD = VB_PGOOD = 0.45 V | 36 | 50 | Ω | |
IVRTTLK | Open-drain leakage current | SDIO, A_PGOOD, B_PGOOD, Hi Z Leakage, 3.3-V applied in off state | –2 | 0.2 | 2 | µA |
VAENL | Channel A ENABLE logic low | 0.7 | V | |||
VAENH | Channel A ENABLE logic high | 0.8 | V | |||
VAENHYS | Channel A ENABLE hysteresis | 0.028 | 0.05 | 0.07 | V | |
tAENDIG | Channel A ENABLE deglitch(1) | 0.2 | µs | |||
IAENH | Channel A I/O 1.1-V leakage | VA_EN = 1.1 V | 25 | µA | ||
VBENL | Channel B ENABLE logic low | 0.7 | V | |||
VBENH | Channel B ENABLE logic high | 0.8 | V | |||
VBENHYS | Channel B ENABLE hysteresis | 0.028 | 0.05 | 0.07 | V | |
tBENDIG | Channel B ENABLE deglitch(1) | 0.2 | µs | |||
tAENVRRDYF | Channel A ENABLE low to A_PGOOD low | From A_EN low to A_PGOOD low | 1.5 | µs | ||
IBENH | Channel B I/O 1.1-V leakage | VBENH = 1.1 V | 25 | µA | ||
VRSTL | RESET logic low | 0.8 | V | |||
VRSTH | RESET logic high(1) | 1.09 | V | |||
tRSTTDLY | RESET delay time | 1 | µs |