10.1 Layout Guidelines

To achieve optimal electrical and thermal performance, an optimized PCB layout is required. Figure 27 thru Figure 30, shows a typical PCB layout. Some considerations for an optimized layout are:

• Use large copper areas for power planes (VIN, VOUT, and PGND) to minimize conduction loss and thermal stress.
• Place ceramic input and output capacitors close to the device pins to minimize high frequency noise.
• Locate additional output capacitors between the ceramic capacitor and the load.
• Keep AGND and PGND separate from one another. The connection is made internal to the device.
• Place R_FBB, R_RT, and C_SS as close as possible to their respective pins.
• Use multiple vias to connect the power planes (VIN, VOUT, and PGND) to internal layers.