The device requires input bypass capacitors between the VIN and PGND pins to bypass the power stage. The bypass capacitors must be placed as close as possible to the pins of the IC as the layout will allow. At least 10-µF of ceramic capacitance is required. Two 0.1-μF and one 1-nF capacitors are integrated inside to the module package, eliminating the need for typical high frequency bypass capacitors. However, they can be used if desired. The high frequency bypass capacitors minimizes high frequency voltage overshoot across the power-stage. The ceramic capacitors must be high-quality dielectric of X6S or better for their high capacitance-to-volume ratio and stable characteristics across temperature. In addition to this, more bulk capacitance can be needed on the input depending on the application to minimize variations on the input voltage during transient conditions.

The input capacitance required to meet a specific input ripple target can be calculated with Equation 19. A recommended target input voltage ripple is 5% the minimum input voltage, 480 mV in this example. The calculated input capacitance is 4.86 μF, and the minimum input capacitance of 10 µF exceeds this. This example meets these two requirements with 2 × 22-µF ceramic capacitors. An input capacitor must be used on both sides of the module during layout, close to pins 5 and 16.

The capacitor must also have an RMS current rating greater than the maximum input RMS current in the application. The input RMS current the input capacitors must support is calculated by Equation 20 and is 4.588 A in this example. The ceramic input capacitors have a current rating greater than this.

For applications requiring bulk capacitance on the input, such as ones with low input voltage and high current, the selection process in this article is recommended.