TPSM8D6C24 devices have three internal linear regulators receiving power from AVIN and providing suitable bias (1.5 V, 1.8 V, and 5 V) for the internal circuitry of the device. Once AVIN, 1.5 V, 1.8 V, and 5 V reach their respective UVLOs, the device initiates a power-on reset, after which, the device can be communicated with through PMBus for configuration and users can store defaults to the NVM.

VDD5 has an internally fixed undervoltage lockout of 3.9 V (typical) to enable power-stage conversion. The VDD5 regulator can also be fed by an external supply of 4.75 V to 5.25 V to reduce internal power dissipation and improve efficiency by eliminating the loss in the internal LDO, or to allow operation with AVIN less than 4 V. The external supply should be higher voltage than the LDO regulation voltage programmed by (B5h) USER_DATA_05 (POWER_STAGE_CONFIG).

The use of the internal regulators to power other circuits is not recommended because the loads placed on the regulators can adversely affect operation of the controller.