ZHCSNL3A December 2021 – November 2023 TPSM8D6C24
PRODUCTION DATA
| CMD Address | 01h |
| Write Transaction: | Write Byte |
| Read Transaction: | Read Byte |
| Format: | Unsigned Binary (1 byte) |
| Phased: | No |
| NVM Backup: | No |
| Updates: | On-the-fly |
The (01h) OPERATION command is used to enable or disable power conversion, in conjunction input from the enable pins, according to the configuration of the (02h) ON_OFF_CONFIG command. This command is also used to set the output voltage to the upper or lower MARGIN levels, and select soft-stop.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RW | RW | RW | RW | RW | RW | RW | R |
| ON_OFF | SOFT_OFF | MARGIN | TRANSITION | 0 | |||
| LEGEND: R/W = Read/Write; R = Read only |
| Bit | Field | Access | Reset | Description |
|---|---|---|---|---|
| 7 | ON_ OFF | RW | 0b | Enable or
disable power conversion when the (02h) ON_OFF_CONFIG command is configured to require input from the CMD
bit for output control. There can be several other requirements that must be
satisfied before the power conversion can begin (for example, input voltages above
UVLO thresholds, enable pins high if required by (02h) ON_OFF_CONFIG, and so forth). 0b: Disable power conversion. 1b: Enable power conversion and enable ignore faults on MARGIN. |
| 6 | SOFT_ OFF | RW | 0b | This bit
controls the turn-off profile when (02h) ON_OFF_CONFIG is configured to require input from the CMD bit for
output voltage control and OPERATION bit 7 transitions from 1b to 0b is ignored when
bit 7 is 1b. 0b: Immediate off. Power conversion stops immediately and the power stage is forced to a high-Z state. 1b: Soft off. Power conversion continues for the tOFF_ DELAY time, then the output voltage is ramped down to 0 V at a slew rate according to tOFF_ FALL. Once the output voltage reaches 0 V, power conversions stops. |
| 5:2 | MARGIN | RW | 0000b | Sets the margin
state. 0000b, 0001b, 0010b: Margin OFF. Output voltage target is (21h) VOUT_COMMAND. OV and UV faults behave normally per their respective fault response settings 0. 0101b: Margin low (ignore fault if bit 7 is 1b). Output voltage target is VOUT_MARGIN_LOW. OV and UV faults are ignored and do not trigger shutdown or STATUS updates. 0110b: Margin low (act on fault). Output voltage target is (26h) VOUT_MARGIN_LOW. OV/UV faults trigger per their respective fault response settings. 1001b: Margin high (ignore fault). Output voltage target is VOUT_MARGIN_HIGH. OV and UV triggers are ignored and do not trigger shutdown or STATUS update. 1010b: Margin high (act on fault). Output voltage target is (25h) VOUT_MARGIN_HIGH. OV/UV trigger per their respective fault response settings. Other: Invalid/unsupported data |
| 1 | TRANSITION | R | 0b | Not used and always set to 0. |
| 0 | Reserved | R | 0b | Not used and always set to 0. |
Attempts to write (01h) OPERATION to any value other than those listed above are considered invalid or unsupported data and cause the TPSM8D6C24 to respond by flagging the appropriate status bits, and notifying the host according to the PMBus 1.3.1 Part II specification, section 10.9.3.