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ZHCSNL3A December 2021 – November 2023 TPSM8D6C24

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6.6.47 (58h) VIN_UV_WARN_LIMIT

CMD Address	58h
Write Transaction:	Write Word
Read Transaction:	Read Word
Format:	SLINEAR11 per CAPABILITY
Phased:	Yes
NVM Backup:	EEPROM
Updates:	On-the-fly

The (58h) VIN_UV_WARN_LIMIT command sets the value of the PVIN pin voltage, in volts, that causes the input voltage detector to indicate an input undervoltage warning.

The (58h) VIN_UV_WARN_LIMIT is a phase command, each phase within a stack independently detects and reports input undervoltage warnings.

In response to an input undervoltage warning condition, the TPSM8D6C24 takes the following action:

Set the NONE OF THE ABOVE bit in the STATUS_BYTE.
Set the INPUT bit in the STATUS_WORD.
Set the VIN_UVW bit in the STATUS_INPUT register.
Notify the host per PMBus 1.3.1 Part II specification, section 10.2.

Figure 6-53 (58h) VIN_UV_WARN_LIMIT Register Map

15	14	13	12	11	10	9	8
RW	RW	RW	RW	RW	RW	RW	RW
VINUVW_EXP					VINUVW_MAN

7	6	5	4	3	2	1	0
RW	RW	RW	RW	RW	RW	RW	RW
VINUVW_MAN

LEGEND: R/W = Read/Write; R = Read only

Table 6-64 Register Field Descriptions

Bit	Field	Access	Reset	Description
15:11	VINUVW_ EXP	RW	11110b	Linear format two’s complement exponent
10:0	VINUVW_ MAN	RW	NVM	Linear format two’s complement mantissa Supported values 2.5 V to 15.5 V

Attempts to write (58h) VIN_UV_WARN_LIMIT to any value outside those specified as valid are considered invalid or unsupported data and cause the TPSM8D6C24 to respond by flagging the appropriate status bits and notifying the host according to the PMBus 1.3.1 Part II specification section 10.9.3.