ZHCSNL3A December 2021 – November 2023 TPSM8D6C24
PRODUCTION DATA
| CMD Address | 47h |
| Write Transaction: | Write Byte |
| Read Transaction: | Read Byte |
| Format: | Unsigned Binary (1 byte) |
| Phased: | No |
| NVM Backup: | EEPROM |
| Updates: | On-the-fly |
The IOUT_OC_FAULT_RESPONSE command instructs the device on what action to take in response to an overcurrent fault. Upon triggering the overcurrent fault, the TPSM8D6C24 responds according to the following data byte, and the following actions are taken:
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RW | RW | RW | RW | RW | R | R | R |
| IO_OC_RESP | IO_OC_RETRY | IO_OC_DELAY | |||||
| LEGEND: R/W = Read/Write; R = Read only |
|
Bit |
Field |
Access |
Reset |
Description |
|---|---|---|---|---|
| 7:6 | IO_OC_RESP | RW | NVM | Output ovecurrent response 00b: Ignore. Continue operating without interruption. 01b: Ignore. Continue operating without interruption. 10b: Shut down after delay as set by IO_OC_DELAY 11b: Shutdown immediately |
| 5:3 | IO_OC_RETRY | RW | NVM | Output overcurrent retry 0d: Do not attempt to restart (latch off). 1d - 6d: After shutting down, wait one HICCUP period, and attempt to restart up to one to six times. After one to six failed restart attempts, do not attempt to restart (latch off). 7d: After shutting down, wait one HICCUP period, and attempt to restart indefinitely until commanded OFF, or a successful start-up occurs. |
| 2:0 | IO_OC_DELAY | RW | NVM | Output overcurrent delay time for respond after delay and
HICCUP 0d: Shutdown delay of one PWM_CLK, HICCUP equal to TON_RISE 1d: Shutdown delay of one PWM_CLK, HICCUP equal to TON_RISE 2d - 4d: Shutdown delay of three PWM_CLK, HICCUP equal to two to four times TON_RISE 5d - 7d: Shutdown delay of seven PWM_CLK, HICCUP equal to five to seven times TON_RISE |
Attempts to write (47h) IOUT_OC_FAULT_RESPONSE to any value outside those specified as valid are considered invalid or unsupported data and cause the TPSM8D6C24 to respond by flagging the appropriate status bits and notifying the host according to the PMBus 1.3.1 Part II specification section 10.9.3.