4 Pin Configuration and Functions

Figure 4-1 59-Pin QFM-MOW Package (Top View)

Figure 4-2 59-Pin QFM-MOW Package (Bottom View)

Table 4-1 Pin Functions

Pin		Type⁽¹⁾	Description
Name	NO.	Type⁽¹⁾	Description
PGND	1, 4, 17, 23, 30, 43, 46, 49, 52, 54, 57, 59	—	Power stage ground return. Pins 52, 54, 57, and 59 also act as the thermal pad of the device.
VOSNS_A	2	I	The positive input of the remote sense amplifier. For a standalone device or a loop controller device in a multi-phase configuration, connect the VOSNS pin to the output voltage at the load. For the loop follower device in a multi-phase configuration, the remote sense amplifier is not required for output voltage sensing or regulation and this pin can be left floating. If used to monitor another voltage with the phased READ_VOUT command, VOSNS must be maintained between 0 V and 0.75 V with a < 1-kΩ resistor divider due to the internal resistance to GOSNS, which is connected to BP1V5.
VOSNS_B	45	I
GOSNS/FLWR_A	3	I	The negative input of the remote sense amplifier for a loop controller device or pull up high to indicate a loop follower. For a standalone device or a loop controller device in a multi-phase configuration, connect the GOSNS pin to the ground at the load. For the loop follower device in a multi-phase configuration, the GOSNS pin must be pulled up to BP1V5 to indicate the device is a loop follower.
GOSNS/FLWR_B	44	I
BP1V5_A	5	O	Output of the 1.5-V internal regulator for MSEL,VSEL, and ADRSEL pins. No external bypassing required. Not designed to power other circuits
BP1V5_B	42	O
SMB_ALRT_A	6	O	SMBus alert pin. See the SMBus specification
SMB_ALRT_B	41	O	SMBus alert pin. See the SMBus specification
PMB_CLK_A	7	I	PMBus CLK pin. See the Current PMBus Specifications.
PMB_CLK_B	40	I	PMBus CLK pin. See the Current PMBus Specifications.
PMB_DATA_A	8	I/O	PMBus DATA pin. See the Current PMBus Specifications.
PMB_DATA_B	39	I/O	PMBus DATA pin. See the Current PMBus Specifications.
PGD/RST_A	9	I/O	Open-drain power good or (21h) VOUT_COMMAND RESET#. As determined by user-programmable RESET# bit in (EDh) MFR_SPECIFIC_29 (MISC_OPTIONS). The default pin function is an open-drain power-good indicator. When configured as RESET#, an internal pullup can be enabled or disabled by the PULLUP# bit in (EDh) MFR_SPECIFIC_29 (MISC_OPTIONS).
PGD/RST_B	38	I/O
BCX_DATA_A	10	I/O	Data for back-channel communications between stacked devices
BCX_DATA_B	37	I/O
BCX_CLK_A	11	I/O	Clock for back-channel communications between stacked devices
BCX_CLK_B	36	I/O
VSHARE_A	12	I/O	Voltage sharing signal for multi-phase operation. For a standalone device, the VSHARE pin must be left floating. VSHARE can by bypassed to AGND with up to 50 pF of capacitance.
VSHARE_B	35	I/O
MSEL1_A	13	I	Connect this pin to a resistor divider between BP1V5and AGND for different options of switching frequency and internal compensation parameters. See the Programming MSEL1 section.
MSEL1_B	34	I
ADRSEL_A	14	I	Connect this pin to a resistor divider between BP1V5 and AGND for different options of PMBus addresses and frequency sync (including determination of SYNC pin as SYNCIN or SYNCOUT function). See the Programming ADRSEL section.
ADRSEL_B	33	I
VSEL_A	15	I	Connect this pin to a resistor divider between BP1V5 and AGND for different options of internal voltage feedback dividers and default output voltage. See Programming VSEL.
VSEL_B	32	I
MSEL2_A	16	I	Connect this pin to a resistor divider between BP1V5 and AGND for different options of soft-start time, overcurrent fault limit, and multiphase information. See the Programming MSEL2 or Programming MSEL2 for a Loop Follower Device (GOSNS Tied to BP1V5) sections for a loop follower device (GOSNS tied to BP1V5) if GOSNS is tied to BP1V5.
MSEL2_B	31	I
EN/UVLO_A	19	I	Enable switching as the PMBus CONTROL pin. EN/UVLO can also be connected to a resistor divider to program input voltage UVLO.
EN/UVLO_B	25	I
PVIN_A	18, 55	I	Input power to the power stage. Low-impedance bypassing of these pins to PGND is critical. PVIN to PGND must be bypassed with X5R or better ceramic capacitors rated for at least 1.5× the maximum PVIN voltage.
PVIN_B	24, 56	I
AVIN_A	20	I	Input power to the controller
AVIN_B	26	I	Input power to the controller
AGND_A	21	—	Analog ground return for controller. Connect the AGND pin directly to the thermal pad on the PCB board.
AGND_B	27	—
VDD5_A	22	O	Output of the 5-V internal regulator. A bypassing capacitor is integrated and no external bypassing is required.
VDD5_B	28	O
SYNC	29	I/O	For frequency synchronization, this pin can be programmed as SYNC IN or SYNC OUT pin by the ADRSEL pin or the (E4h) MFR_SPECIFIC_20 (SYNC_CONFIG) PMBus command. SYNC is tied together internally for phase A and B. SYNC pin can be left floating when using module in single-phase configuration.
VOUT_A	50, 51	O	Output of each channel. Connect to output bypass capacitors to this pin.
VOUT_B	47, 48	O
Thermal Pad	52, 54, 57, 59	—	The thermal pad is the PGND pin made with a large area of copper to improve thermal conductivity to PCB. The thermal pad must have adequate solder coverage for best thermal performance.
SW_A	53	I/O	Switched power output of the device. Connect the output averaging filter and bootstrap to this group of pins if needed.
SW_B	58	I/O

(1) I = input, O = output