The TPSM8S6C24 limits current from being discharged from a pre-biased output voltage during start-up by preventing the low-side FET from forcing the SW node low until after the first PWM pulse turns on the high-side FET. After VOSNS voltage exceeds the increasing reference voltage and high-side SW pulses start, the TPSM8S6C24 limits the synchronous rectification during each SW period with a narrow on time. The maximum low-side MOSFET on time slowly increases on a cycle-by-cycle basis until 128 switching periods have elapsed and the synchronous rectifier runs fully complementary to the high-side MOSFET. This limits the sinking of current from a pre-biased output, and makes sure the output voltage start-up and ramp-to regulation sequences are monotonically increasing.

In the event of a pre-biased output voltage greater than (40h) VOUT_OV_FAULT_LIMIT, the TPSM8S6C24 responds as soon as it completes POR and VDD5 is greater than its own 3.9-V UVLO, even if conversion is disabled by EN/UVLO or the PMBus (01h) OPERATION command.