ZHCSRQ4 august 2023 TPSM8S6C24
PRODUCTION DATA
| CMD Address | EEh |
| Write Transaction: | Write Word |
| Read Transaction: | Read Word |
| Format: | Unsigned Binary (1 byte) |
| Phased: | No |
| NVM Backup: | EEPROM |
| Updates: | on-the-fly (pin detection occurs on POR only). |
PMBUS specified that NVM (Default or User) stored values will overwrite Pin Programmed Values. Setting a “1” in each bit of this register will prevent DEFAULT or USER STORE values from overwriting the Pin-Programmed Value associated that bit.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RW | RW | RW | RW | RW | RW | RW | RW |
| Reserved | STACK_CONFIG | SYNC_CONFIG | Reserved | COMP_CONFIG | ADDRESS | ||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RW | RW | RW | RW | RW | RW | RW | RW |
| Reserved | INTERLEAVE | Reserved | TON_RISE | IOUT_OC | FREQ | VOUT | |
| LEGEND: R/W = Read/Write; R = Read only |
| Bit | Field | Access | Reset | Description |
|---|---|---|---|---|
| 15:13 | Reserved | RW | NVM | Not used and set to 000b. |
| 12 | STACK_CONFIG | RW | NVM | 0b: At power-up or RESTORE, STACK_CONFIG will be reset to NVM value. 1b: At power-up or RESTORE, STACK_CONFIG will be reset to pin-detected value. |
| 11 | SYNC_CONFIG | RW | NVM | 0b: At power-up or RESTORE, SYNC_CONFIG will be reset to NVM value. 1b: At power-up or RESTORE, SYNC_CONFIG will be reset to pin-detected value. |
| 10 | Reserved | RW | NVM | Not used and set to 0b or 1b. |
| 9 | COMP_CONFIG | RW | NVM | 0b: At power-up or RESTORE, COMPENSATION_CONFIG will be reset to NVM value. 1b: At power-up or RESTORE, COMPENSATION_CONFIG will be reset to pin-detected value. |
| 8 | ADDRESS | RW | NVM | 0b: At power-up or RESTORE, Loop Follower_ADDRESS will be reset to NVM value. 1b: At power-up or RESTORE, Loop Follower_ADDRESS will be reset to pin-detected value. |
| 7:6 | Reserved | RW | NVM | Not used and set to 00b. |
| 5 | INTERLEAVE | RW | NVM | 0b: At power-up or RESTORE, INTERLEAVE will be reset to NVM value. 1b: At power-up or RESTORE, INTERLEAVE will be reset to pin-detected value. |
| 4 | Reserved | RW | NVM | Not used and set to 0b or 1b. |
| 3 | TON_RISE | RW | NVM | 0b: At power-up or RESTORE, TON_RISE will be reset to NVM value. 1b: At power-up or RESTORE, TON_RISE will be reset to pin-detected value. |
| 2 | IOUT_OC | RW | NVM | 0b: At power-up or RESTORE, IOUT_OC_FAULT_LIMIT and IOUT_OC_WARN_LIMIT will be
reset to NVM value. 1b: At power-up or RESTORE, IOUT_OC_FAULT_LIMIT and IOUT_OC_WARN_LIMIT will be reset to pin-detected value. |
| 1 | FREQ | RW | NVM | 0b: At power-up or RESTORE, FREQUENCY_SWITCH will be reset to NVM value. 1b: At power-up or RESTORE, FREQUENCY_SWITCH will be reset to pin-detected value. |
| 0 | VOUT | RW | NVM | 0b: At power-up or RESTORE, VOUT_COMMAND, VOUT_SCALE_LOOP, VOUT_MAX, and VOUT_MIN
will be reset to NVM value. 1b: At power-up or RESTORE, VOUT_COMMAND, VOUT_SCALE_LOOP, VOUT_MAX, and VOUT_MIN will be reset to pin-detected value. |
PIN_DETECT_OVERRIDE allows the user to force Pin Detected values to override the User Store NVM value for various PMBus commands during Power On Reset and RESTORE_USER_ALL.