7.1 Serial Interface Timing Diagram

The TRF3722 features a four-wire serial programming interface (4WI) that controls an internal 32-bit shift register with seven parallel registers. There are total of three signals that must be applied: the clock (CLK), the serial data (DATA), and the latch enable (LE). The fouth signal is the read back (RDBK) signal. The serial data (DB0-DB31) are loaded least significant bit (LSB) first, and read on the rising edge of the CLK. LE is asynchronous to the CLK signal; at its rising edge, the data in the shift register are loaded into the selected internal register. Figure 130 shows the timing diagram the 4WI. Table 1 lists the 4WI timing for the write operation.

Figure 130. 4WI Writing Timing Diagram

TRF3722 integrates 7 registers: Register 0 (000) to Register 6 (110). Registers 1 through 6 are used to set-up and control the TRF3722 functionalities, while register 0 is used for the read-back function. Each read-back is composed by two phases: writing followed by the actual reading of the internal data. This is shown in the timing diagram in Figure 131.

Figure 131. 4WI Read-Back Timing Diagram

During the writing phase a command is sent to TRF3722 register 0 to set it in read-back mode and to specify which register is to be read. In the proper reading phase, at each rising clock edge, the internal data is transferred into the RDBK pin and can be read at the following falling edge (LSB first). The first clock after the LE goes high (end of writing cycle) is idle and the following 32 clocks pulses will transfer the internal register content to the RDBK pin. Table 2 shows the Readback timing.