6.8 Oscillator Section

The 13.56-MHz oscillator is controlled by the Chip Status Control register (0x00) and the EN and EN2 signals. The oscillator generates the RF frequency for the RF output stage and the clock source for the digital section. The buffered clock signal is available at pin 27 (SYS_CLK) for external circuits. B4 and B5 inside the Modulation and SYS_CLK register (0x09) can be used to divide the external SYS_CLK signal at pin 27 by 1, 2, or 4.

Typical start-up time from complete power down is in the range of 3.5 ms.

During Power Down Mode 2 (EN = 0, EN2 = 1) the frequency of SYS_CLK is switched to 60 kHz (typical).

The 13.56-MHz crystal must be connected between pin 30 and pin 31. The external shunt capacitors values for C₁ and C₂ must be calculated based on the specified load capacitance of the crystal being used. The external shunt capacitors are calculated as two identical capacitors in series plus the stray capacitance of the TRF7960A and parasitic PCB capacitance in parallel to the crystal.

The parasitic capacitance (C_S , stray and parasitic PCB capacitance) can be estimated at 4 to 5 pF (typical).

As an example, using a crystal with a required load capacitance (C_L) of 18 pF, the calculation is as follows (see Figure 6-4):

C₁= C₂ = 2 × (C_L – C_S) = 2 × (18 pF – 4.5 pF) = 27 pF

Place a 27-pF capacitor on pins 30 and 31 to ensure proper crystal oscillator operation.

Figure 6-4 Crystal Block Diagram

Table 6-5 shows the minimum characteristics recommended for any crystal used with TRF7960A.

As an alternative, an external clock oscillator source can be connected to pin 31 to provide the system clock, and pin 30 can be left open.