6.12.6 Serial Interface Communication (SPI)

When an SPI interface is used, I/O pins I/O_2, I/O_1, and I/O_0 must be hard-wired as specified in Table 6-6. On power up, the TRF7960A looks for the status of these pins; if they are not the same (not all high, or not all low), the reader enters into one of two possible SPI modes:

• SPI with slave select

or

• SPI without slave select

The choice of one of these modes over the other should be made based on the available GPIOs and the desired control of the system.

The serial communications work in the same manner as the parallel communications with respect to the FIFO, except for the following condition. On receiving an IRQ from the reader, the MCU reads the TRF7960A IRQ Status register to determine how to service the reader. After this, the MCU must to do a dummy read to clear the reader's IRQ Status register. The dummy read is required in SPI mode, because the reader's IRQ Status register needs an additional clock cycle to clear the register. This is not required in parallel mode, because the additional clock cycle is included in the Stop condition.

A procedure for a dummy read is as follows:

1. Starting the dummy read
   1. When using slave select (SS): set SS bit low
   2. When not using SS: start condition is when SCLK is high
2. Send address word to IRQ Status register (0x0C) with read and continuous address mode bits set to 1
3. Read 1 byte (8 bits) from IRQ Status register (0x0C)
4. Dummy read 1 byte from register 0Dh (collision position and interrupt mask)
5. Stopping the dummy read
   1. When using slave select (SS): set SS bit high
   2. When not using SS: stop condition when SCLK is high

Figure 6-14 Procedure for Dummy Read

Figure 6-15 Dummy Read Using SPI With SS