ZHCS266F June 2011 – May 2017 TRF7960A
PRODUCTION DATA.
Table 6-22 describes the bit fields of the TX Timer Low Byte Control register. This register sets timings.
Default Value: 0x00, set at POR = H or EN = L and at each write to the ISO Control register
| BIT NO. | BIT NAME | FUNCTION | DESCRIPTION |
|---|---|---|---|
| B7 | tm_length7 | Timer length MSB | Defines the time when delayed transmission is started. RX wait range is 590 ns to 9.76 ms (1 to 16383), Step size is 590 ns, All bits low = timer disabled (0x00) Preset to 0x00 for all other protocols. |
| B6 | tm_length6 | Timer length | |
| B5 | tm_length5 | Timer length | |
| B4 | tm_length4 | Timer length | |
| B3 | tm_length3 | Timer length | |
| B2 | tm_length2 | Timer length | |
| B1 | tm_length1 | Timer length | |
| B0 | tm_length0 | Timer length LSB |