ZHCS266F June   2011  – May 2017 TRF7960A

PRODUCTION DATA.  

  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
    4. 1.4 应用框图
  2. 2修订历史记录
  3. 3Device Characteristics
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Electrical Characteristics
    5. 5.5 Thermal Resistance Characteristics
    6. 5.6 Switching Characteristics
  6. 6Detailed Description
    1. 6.1  Functional Block Diagram
    2. 6.2  Power Supplies
    3. 6.3  Supply Arrangements
    4. 6.4  Supply Regulator Settings
    5. 6.5  Power Modes
    6. 6.6  Receiver – Analog Section
      1. 6.6.1 Main and Auxiliary Receiver
      2. 6.6.2 Receiver Gain and Filter Stages
    7. 6.7  Receiver – Digital Section
      1. 6.7.1 Received Signal Strength Indicator (RSSI)
        1. 6.7.1.1 Internal RSSI – Main and Auxiliary Receivers
        2. 6.7.1.2 External RSSI
    8. 6.8  Oscillator Section
    9. 6.9  Transmitter - Analog Section
    10. 6.10 Transmitter - Digital Section
    11. 6.11 Transmitter – External Power Amplifier or Subcarrier Detector
    12. 6.12 Communication Interface
      1. 6.12.1 General Introduction
      2. 6.12.2 FIFO Operation
      3. 6.12.3 Parallel Interface Mode
      4. 6.12.4 Reception of Air Interface Data
      5. 6.12.5 Data Transmission to MCU
      6. 6.12.6 Serial Interface Communication (SPI)
        1. 6.12.6.1 Serial Interface Mode Without Slave Select (SS)
        2. 6.12.6.2 Serial Interface Mode With Slave Select (SS)
      7. 6.12.7 Direct Mode
    13. 6.13 Direct Commands from MCU to Reader
      1. 6.13.1  Command Codes
      2. 6.13.2  Reset FIFO (0x0F)
      3. 6.13.3  Transmission With CRC (0x11)
      4. 6.13.4  Transmission Without CRC (0x10)
      5. 6.13.5  Delayed Transmission With CRC (0x13)
      6. 6.13.6  Delayed Transmission Without CRC (0x12)
      7. 6.13.7  Transmit Next Time Slot (0x14)
      8. 6.13.8  Block Receiver (0x16)
      9. 6.13.9  Enable Receiver (0x17)
      10. 6.13.10 Test Internal RF (RSSI at RX Input With TX On) (0x18)
      11. 6.13.11 Test External RF (RSSI at RX Input With TX Off) (0x19)
      12. 6.13.12 Register Preset
    14. 6.14 Register Description
      1. 6.14.1 Register Overview
        1. 6.14.1.1 Main Configuration Registers
          1. 6.14.1.1.1 Chip Status Control Register (0x00)
          2. 6.14.1.1.2 ISO Control Register (0x01)
        2. 6.14.1.2 Protocol Subsetting Registers
          1. 6.14.1.2.1  ISO14443B TX Options Register (0x02)
          2. 6.14.1.2.2  ISO14443A High-Bit-Rate and Parity Options Register (0x03)
          3. 6.14.1.2.3  TX Timer High Byte Control Register (0x04)
          4. 6.14.1.2.4  TX Timer Low Byte Control Register (0x05)
          5. 6.14.1.2.5  TX Pulse Length Control Register (0x06)
          6. 6.14.1.2.6  RX No Response Wait Time Register (0x07)
          7. 6.14.1.2.7  RX Wait Time Register (0x08)
          8. 6.14.1.2.8  Modulator and SYS_CLK Control Register (0x09)
          9. 6.14.1.2.9  RX Special Setting Register (0x0A)
          10. 6.14.1.2.10 Regulator and I/O Control Register (0x0B)
        3. 6.14.1.3 Status Registers
          1. 6.14.1.3.1 IRQ Status Register (0x0C)
          2. 6.14.1.3.2 Collision Position and Interrupt Mask Registers (0x0D and 0x0E)
          3. 6.14.1.3.3 RSSI Levels and Oscillator Status Register (0x0F)
        4. 6.14.1.4 Test Registers
          1. 6.14.1.4.1 Test Register (0x1A)
          2. 6.14.1.4.2 Test Register (0x1B)
        5. 6.14.1.5 FIFO Control Registers
          1. 6.14.1.5.1 FIFO Status Register (0x1C)
          2. 6.14.1.5.2 TX Length Byte1 Register (0x1D) and TX Length Byte2 Register (0x1E)
  7. 7Applications, Implementation, and Layout
    1. 7.1 TRF7960A Reader System Using SPI With SS Mode
      1. 7.1.1 General Application Considerations
      2. 7.1.2 Schematic
    2. 7.2 System Design
      1. 7.2.1 Layout Considerations
      2. 7.2.2 Impedance Matching TX_Out (Pin 5) to 50 Ω
      3. 7.2.3 Reader Antenna Design Guidelines
  8. 8器件和文档支持
    1. 8.1 入门和后续步骤
    2. 8.2 器件命名规则
    3. 8.3 工具和软件
    4. 8.4 文档支持
    5. 8.5 社区资源
    6. 8.6 商标
    7. 8.7 静电放电警告
    8. 8.8 出口管制提示
    9. 8.9 Glossary
  9. 9机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.14.1.4.2 Test Register (0x1B)

Table 6-38 describes the bit fields of the Test register at 0x1B. When a test_dec or test_io is set, the IC is switched to test mode. Test mode persists until a stop condition arrives. At stop condition, the test_dec and test_io bits are cleared.

Default Value: 0x00, set at POR = H and EN = L

Table 6-38 Test Register 2 (0x1B) (for Test or Direct Use)

BIT NO. BIT NAME FUNCTION DESCRIPTION
B7 test_rf_level RF level test
B6
B5
B4
B3 test_io1 I/O test Not implemented
B2 test_io0
B1 test_dec Decoder test mode
B0 clock_su Coder clock 13.56 MHz For faster test of coders
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