6.14.1.5.2 TX Length Byte1 Register (0x1D) and TX Length Byte2 Register (0x1E)
Table 6-40 describes the bit fields of the TX Length Byte1 register. This register contains the high two nibbles of complete intended bytes to be transferred through FIFO.
Default Value: 0x00, set at POR and EN = 0. The register is also automatically reset at TX EOF.
Table 6-40 TX Length Byte1 Register (0x1D)
| BIT NO. | BIT NAME | FUNCTION | DESCRIPTION |
|---|
| B7 |
Txl11 |
Number of complete byte bn[11] |
High nibble of complete intended bytes to be transmitted |
| B6 |
Txl10 |
Number of complete byte bn[10] |
| B5 |
Txl9 |
Number of complete byte bn[9] |
| B4 |
Txl8 |
Number of complete byte bn[8] |
| B3 |
Txl7 |
Number of complete byte bn[7] |
Middle nibble of complete intended bytes to be transmitted |
| B2 |
Txl6 |
Number of complete byte bn[6] |
| B1 |
Txl5 |
Number of complete byte bn[5] |
| B0 |
Txl4 |
Number of complete byte bn[4] |
Table 6-41 describes the bit fields of the TX Length Byte2 register. This register contains the low nibble of the complete bytes to be transferred through FIFO, and information about a broken byte and number of bits to be transferred from it.
Default Value: 0x00, set at POR and EN = 0. The register is also automatically reset at TX EOF.
Table 6-41 TX Length Byte2 Register (0x1E)
| BIT NO. | BIT NAME | FUNCTION | DESCRIPTION |
|---|
| B7 |
Txl3 |
Number of complete byte bn[3] |
Low nibble of complete intended bytes to be transmitted |
| B6 |
Txl2 |
Number of complete byte bn[2] |
| B5 |
Txl1 |
Number of complete byte bn[1] |
| B4 |
Txl0 |
Number of complete byte bn[0] |
| B3 |
Bb2 |
Broken byte number of bits bb[2] |
Number of bits in the last broken byte to be transmitted. This value is taken into account only when broken byte flag is set.
|
| B2 |
Bb1 |
Broken byte number of bits bb[1] |
| B1 |
Bb0 |
Broken byte number of bits bb[0] |
| B0 |
Bbf |
Broken byte flag |
B0 = 1 indicates that last byte is not complete 8 bits wide. |