6.5 Power Modes

The chip has several power states, which are controlled by two input pins (EN and EN2) and several bits in the Chip Status Control register (0x00).

Table 6-3 lists the configuration for the different power modes when using a 5-V or 3-V system supply. The main reader enable signal is pin EN. When EN is set high, all of the reader regulators are enabled, the 13.56-MHz oscillator is running, and the SYS_CLK (output clock for external microcontroller) is also available.

The Regulator Control register settings shown are for optimized power out. The automatic setting (normally 0x87) is optimized for best PSRR and noise reduction.

The input pin EN2 has two functions:

• A direct connection from EN2 to VIN to ensure the availability of the regulated supply VDD_X and an auxiliary clock signal (60 kHz, SYS_CLK) for an external MCU. This mode (EN = 0, EN2 = 1) is intended for systems in which the MCU is also being supplied by the reader supply regulator (VDD_X) and the MCU clock is supplied by the SYS_CLK output of the reader. This lets the MCU supply and clock be available during sleep mode.
• EN2 enables the start-up of the reader system from complete power down (EN = 0, EN2 = 0). In this case, the EN input is being controlled by the MCU (or other system device) that is without supply voltage during complete power down (thus unable to control the EN input). A rising edge applied to the EN2 input (which has an approximately 1-V threshold level) starts the reader supply system and 13.56‑MHz oscillator (identical to condition EN = 1).

When the user MCU controls EN and EN2, use a delay of 5 ms between EN and EN2. When the MCU controls only EN, TI recommends connecting EN2 to either VIN or GND, depending on the application MCU requirements for VDD_X and SYS_CLK.

This start-up mode lasts until all of the regulators have settled and the 13.56-MHz oscillator has stabilized. If the EN input is set high (EN = 1) by the MCU (or other system device), the reader stays active. If the EN input is not set high (EN = 0) within 100 µs after the SYS_CLK output is switched from auxiliary clock (60 kHz) to high-frequency clock (derived from the crystal oscillator), the reader system returns to complete Power-Down Mode 1. This option can be used to wake the reader system from complete power down (PD Mode 1) by using a push-button switch or by sending a single pulse.

After the reader EN line is high, the other power modes are selected by control bits within the Chip Status Control register (0x00). The power mode options and states are listed in Table 6-3.

When EN is set high (or on rising edge of EN2 and then confirmed by EN = 1) the supply regulators are activated and the 13.56-MHz oscillator started. When the supplies are settled and the oscillator frequency is stable, the SYS_CLK output is switched from the auxiliary frequency of 60 kHz to the 13.56-MHz frequency derived from the crystal oscillator. At this time, the reader is ready to communicate and perform the required tasks. The MCU can then program the Chip Status Control register 0x00 and select the operation mode by programming the additional registers.

• Standby mode (bit 7 = 1 of register 0x00), the reader is capable of recovering to full operation in 100 µs.
• Mode 1 (active mode with RF output disabled, bit 5 = 0 and bit 1 = 0 of register 0x00) is a low-power mode that lets the reader recover to full operation within 25 µs.
• Mode 2 (active mode with only the RF receiver active, bit 1 = 1 of register 0x00) can be used to measure the external RF field (as described in RSSI measurements paragraph) if reader-to-reader anticollision is implemented.
• Mode 3 and Mode 4 (active modes with the entire RF section active, bit 5 = 1 of register 0x00) are the modes used for typical transmit and receive operations.