ZHCS762F December 2011 – May 2017 TRF7963A
PRODUCTION DATA.
Table 6-31 describes the bit fields of the IRQ Status register. This register provides information available about TRF7963A IRQ, TX, and RX status.
Default Value: 0x00, set at POR = H or EN = L and at each write to the ISO Control register (0x01). The register is also automatically reset at the end of a read phase. The reset also removes the IRQ flag.
To reset (clear) the register and the IRQ line, the register must be read. During transmit, the decoder is disabled, and only bits B5 and B7 can be changed. During receive, only bit B6 can be changed, but does not trigger the IRQ line immediately. The IRQ signal is set at the end of the transmit or receive phase.
| BIT NO. | BIT NAME | FUNCTION | DESCRIPTION |
|---|---|---|---|
| B7 | Irq_tx | IRQ set due to end of TX | Signals that TX is in progress. The flag is set at the start of TX but the interrupt request (IRQ = 1) is sent when TX is finished. |
| B6 | Irg_srx | IRQ set due to RX start | Signals that RX SOF was received and RX is in progress. The flag is set at the start of RX but the interrupt request (IRQ = 1) is sent when RX is finished. |
| B5 | Irq_fifo | FIFO is high or low | Signals when the FIFO is high or low (more than 8 bits during RX or less than 4 bits during TX). See Section 6.12.2 for details. |
| B4 | Irq_err1 | CRC error | Indicates receive CRC error only if B7 (no RX CRC) of ISO Control register is set to 0. |
| B3 | Irq_err2 | Parity error | Indicates parity error for ISO/IEC 14443 A |
| B2 | Irq_err3 | Byte framing or EOF error | Indicates framing error |
| B1 | Irq_col | Collision error | Collision error for ISO/IEC 14443 A . Bit is set if more then 6 or 7 (as defined in register 0x01) are detected inside 1 bit period of ISO/IEC 14443 A 106 kbps. Collision error bit can also be triggered by external noise. |
| B0 | Irq_noresp | No-response time interrupt | No response within the "No-response time" defined in RX No-response Wait Time register (0x07). |