6.1.1 RFID – Reader and Writer

The is a high-performance 13.56-MHz HF RFID transceiver IC composed of an integrated analog front end (AFE) and a built-in data framing engine for ISO/IEC 15693, ISO/IEC 14443 A and B, and FeliCa. This includes data rates up to 848 kbps for ISO/IEC 14443 with all framing and synchronization tasks on board (in default mode). This architecture lets the customer build a complete cost-effective yet high-performance multiprotocol 13.56-MHz RFID system together with a low-cost microcontroller.

Other standards and even custom protocols can be implemented by using either of the direct modes that the device offers. These direct modes (0 and 1) allow the user to fully control the analog front end (AFE) and also gain access to the raw subcarrier data or the unframed but already ISO formatted data and the associated (extracted) clock signal.

The receiver system has a dual input receiver architecture. The receivers also include various automatic and manual gain control options. The received input bandwidth can be selected to cover a broad range of input subcarrier signal options.

The received signal strength from transponders, ambient sources, or internal levels is available through the RSSI register. The receiver output is selectable among a digitized subcarrier signal and any of the integrated subcarrier decoders. The selected subcarrier decoder delivers the data bit stream and the data clock as outputs.

The TRF7964A also includes a receiver framing engine. This receiver framing engine performs the CRC or parity check, removes the EOF and SOF settings, and organizes the data in bytes for ISO/IEC 14443 A and B, ISO/IEC 15693, and FeliCa protocols. Framed data is then accessible to the microcontroller (MCU) through a 127-byte FIFO register.

Figure 6-1 Application Block Diagram

A parallel or serial interface (SPI) can be used for the communication between the MCU and the TRF7964A reader. When the built-in hardware encoders and decoders are used, transmit and receive functions use a 127-byte FIFO register. For direct transmit or receive functions, the encoders and decoders can be bypassed so that the MCU can process the data in real time. The TRF7964A supports data communication voltage levels from 1.8 V to 5.5 V for the MCU I/O interface. The transmitter has selectable output-power levels of 100 mW (+20 dBm) or 200 mW (+23 dBm) equivalent into a 50-Ω load when using a 5-V supply.

The transmitter supports OOK and ASK modulation with selectable modulation depth. The TRF7964A also includes a data transmission engine that comprises low-level encoding for ISO/IEC 15693, ISO/IEC 14443 A and B, and FeliCa. Included with the transmit data coding is the automatic generation of Start Of Frame (SOF), End Of Frame (EOF), Cyclic Redundancy Check (CRC), and parity bits.

Several integrated voltage regulators ensure a proper power-supply noise rejection for the complete reader system. The built-in programmable auxiliary voltage regulator V_{DD_X} (pin 32), is able to deliver up to 20 mA to supply a microcontroller and additional external circuits within the reader system.

6.3.1 Supply Arrangements

Regulator Supply Input: V_IN

The positive supply at V_IN (pin 2) has an input voltage range of 2.7 V to 5.5 V. V_IN provides the supply input sources for three internal regulators with the output voltages V_{DD_RF}, V_{DD_A}, and V_{DD_X}. External bypass capacitors for supply noise filtering must be used (per reference schematics).

RF Power Amplifier Regulator: V_{DD_RF}

The V_{DD_RF} (pin 3) regulator is supplying the RF power amplifier. The voltage regulator can be set for either 5-V or 3-V operation. External bypass capacitors for supply noise filtering must be used (per reference schematics). When configured for 5-V manual-operation, the V_{DD_RF} output voltage can be set from 4.3 V to 5 V in 100-mV steps. In 3-V manual-operation, the output can be programmed from 2.7 V to 3.4 V in 100-mV steps. The maximum output current capability for 5-V operation is 150 mA and for 3-V operation is 100 mA.

Analog Supply Regulator: V_{DD_A}

Regulator V_{DD_A} (pin 1) supplies the analog circuits of the device. The output voltage setting depends on the input voltage and can be set for 5-V and 3-V operation. When configured for 5-V manual-operation, the output voltage is fixed at 3.4 V. External bypass capacitors for supply noise filtering must be used (per reference schematics). When configured for 3-V manual-operation, the V_{DD_A} output can be set from 2.7 V to 3.4 V in 100-mV steps (see Table 6-2).

Digital Supply Regulator: V_{DD_X}

The digital supply regulator V_{DD_X} (pin 32) provides the power for the internal digital building blocks and can also be used to supply external electronics within the reader system. When configured for 3-V operation, the output voltage can be set from 2.7 to 3.4 V in 100-mV steps. External bypass capacitors for supply noise filtering must be used (per reference schematics).

By default, the regulators are set in automatic regulator setting mode. In this mode, the regulators are automatically set every time the system is activated by setting EN input High or each time the automatic regulator setting bit, B7 in register 0x0B is set to a 1. The action is started on the 0 to 1 transition. This means that, if the user wants to rerun the automatic setting from a state in which the automatic setting bit is already high, the automatic setting bit (B7 in register 0x0B) should be changed: 1-0-1.

By default, the regulator setting algorithm sets the regulator outputs to a "Delta Voltage" of 400 mV below V_IN, but not higher than 5 V for V_{DD_RF} and 3.4 V for V_{DD_A} and V_{DD_A}.

Power Amplifier Supply: V_{DD_PA}

The power amplifier of the TRF7964A is supplied through V_{DD_PA} (pin 4). The positive supply pin for the RF power amplifier is externally connected to the regulator output V_{DD_RF} (pin 3).

I/O Level Shifter Supply: V_{DD_I/O}

The TRF7964A has a separate supply input V_{DD_I/O} (pin 16) for the built-in I/O level shifter. The supported input voltage ranges from 1.8 V to V_IN, not exceeding 5.5 V. Pin 16 is used to supply the I/O interface pins (I/O_0 to I/O_7), IRQ, SYS_CLK, and DATA_CLK pins of the reader. In typical applications, V_{DD_I/O} is directly connected to V_{DD_X}, while V_{DD_X} also supplies the MCU. This ensures that the I/O signal levels of the MCU match the logic levels of the TRF7964A.

Negative Supply Connections: V_SS, V_{SS_TX}, V_{SS_RX}, V_{SS_A}, V_{SS_PA}

The negative supply connections V_{SS_X} of each functional block are all externally connected to GND.

The substrate connection is V_SS (pin 10), the analog negative supply is V_{SS_A} (pin 15), the logic negative supply is V_{SS_D} (pin 29), the RF output stage negative supply is V_{SS_PA} (pin 6), and the negative supply for the RF receiver V_{SS_RX} (pin 7).

6.3.2 Supply Regulator Settings

The input supply voltage mode of the reader needs to be selected. This is done in the Chip Status Control register (0x00). Bit 0 in register 0x00 selects between 5-V or 3-V input supply voltage. The default configuration is 5 V, which reflects an operating supply voltage range of 4.3 V to 5.5 V. If the supply voltage is below 4.3 V, the 3-V configuration should be used.

As V_{DD_RF} is increased, the system can become more susceptible to noise coupling on the RX lines. For minimum noise coupling, TI recommends using the value of 0x00. For improved range, higher V_{DD_RF} voltages may be set, but complete system testing is required to determine the value which provides optimal performance.

The various regulators can be configured to operate in automatic or manual mode. This is done in the Regulator and I/O Control register (0x0B), as shown in Table 6-1 and Table 6-2.

The regulator configuration function adjusts the regulator outputs by default to 400 mV below V_IN level, but not higher than 5 V for V_{DD_RF}, 3.4 V for V_{DD_A} and V_{DD_X}. This ensures the highest possible supply voltage for the RF output stage while maintaining an adequate PSRR (power supply rejection ratio).

6.3.3 Power Modes

The chip has several power states, which are controlled by two input pins (EN and EN2) and several bits in the chip status control register (0x00) (see Table 6-3 and Table 6-4).

Table 6-3 and Table 6-4 show the configuration for the different power modes when using a 3.3-V or 5-V system supply, respectively. The main reader enable signal is pin EN. When EN is set high, all of the reader regulators are enabled, the 13.56-MHz oscillator is running and the SYS_CLK (output clock for external microcontroller) is also available.

The input pin EN2 has two functions:

• A direct connection from EN2 to V_IN to ensure the availability of the regulated supply V_{DD_X} and an auxiliary clock signal (60 kHz, SYS_CLK) for an external MCU. This mode (EN = 0, EN2 = 1) is intended for systems in which the MCU is also being supplied by the reader supply regulator (V_{DD_X}) and the MCU clock is supplied by the SYS_CLK output of the reader. This allows the MCU supply and clock to be available during sleep mode.
• EN2 enables the start-up of the reader system from complete power down (EN = 0, EN2 = 0). In this case the EN input is being controlled by the MCU (or other system device) that is without supply voltage during complete power down (thus unable to control the EN input). A rising edge applied to the EN2 input (which has an approximately 1-V threshold level) starts the reader supply system and 13.56-MHz oscillator (identical to condition EN = 1).

When user MCU is controlling EN and EN2, a delay of 1 ms between EN and EN2 must be used. If the MCU controls only EN, TI recommends connecting EN2 to either V_IN or GND, depending on the application MCU requirements for V_{DD_X} and SYS_CLK.

Figure 6-3 Nominal Start-up Sequence Using SPI With SS (MCU Controls EN2)

Figure 6-4 Nominal Start-up Sequence Using Parallel (MCU Controls EN2)

This start-up mode lasts until all of the regulators have settled and the 13.56-MHz oscillator has stabilized. If the EN input is set high (EN = 1) by the MCU (or other system device), the reader stays active. If the EN input is not set high (EN = 0) within 100 µs after the SYS_CLK output is switched from auxiliary clock (60 kHz) to high-frequency clock (derived from the crystal oscillator), the reader system returns to complete Power-Down Mode 1. This option can be used to wake-up the reader system from complete Power Down (PD Mode 1) by using a pushbutton switch or by sending a single pulse.

After the reader EN line is high, the other power modes are selected by control bits within the chip status control register (0x00). The power mode options and states are listed in Table 6-3.

When EN is set high (or on rising edge of EN2 and then confirmed by EN = 1) the supply regulators are activated and the 13.56-MHz oscillator is started. When the supplies are settled and the oscillator frequency is stable, the SYS_CLK output is switched from the auxiliary frequency of 60 kHz to the 13.56-MHz frequency derived from the crystal oscillator. At this point, the reader is ready to communicate and perform the required tasks. When this occurs, osc_ok (B6) of the RSSI Level and Oscillator Status register is set. The MCU can then program the Chip Status Control register 0x00 and select the operation mode by programming the additional registers.

• Standby Mode (bit 7 = 1 of register 0x00), the reader is capable of recovering to full operation in 100 µs.
• Mode 1 (active mode with RF output disabled, bit 5 = 0 and bit 1 = 0 of register 0x00) is a low power mode which allows the reader to recover to full operation within 25 µs.
• Mode 2 (active mode with only the RF receiver active, bit 1 = 1 of register 0x00) can be used to measure the external RF field (as described in RSSI measurements paragraph) if reader-to-reader anticollision is implemented.
• Modes 3 and 4 (active modes with the entire RF section active, bit 5 = 1 of register 0x00) are the normal modes used for normal transmit and receive operations.

6.4.1 Main and Auxiliary Receivers

The TRF7964A has two receiver inputs: RX_IN1 (pin 8) and RX_IN2 (pin 9). Each of the input is connected to an external capacitive voltage divider to ensure that the modulated signal from the tag is available on at least one of the two inputs. This architecture eliminates any possible communication holes that may occur from the tag to the reader.

The two RX inputs (RX_IN1 and RX_IN2) are multiplexed into two receivers - the main receiver and the auxiliary receiver. Only the main receiver is used for reception, the auxiliary receiver is used for signal quality monitoring. Receiver input multiplexing is controlled by bit B3 in the Chip Status Control register (address 0x00).

After start-up, RX_IN1 is multiplexed to the main receiver which is composed of an RF envelope detection, first gain and band-pass filtering stage, second gain and filtering stage with AGC. Only the main receiver is connected to the digitizing stage which output is connected to the digital processing block. The main receiver also has an RSSI measuring stage, which measures the strength of the demodulated signal (subcarrier signal).

The primary function of the auxiliary receiver is to monitor the RX signal quality by measuring the RSSI of the demodulated subcarrier signal (internal RSSI). After start-up, RX_IN2 is multiplexed to the auxiliary receiver. The auxiliary receiver has an RF envelope detection stage, first gain and filtering with AGC stage and finally the auxiliary RSSI block.

The default MUX setting is RX_IN1 connected to the main receiver and RX_IN2 connected to the auxiliary receiver. To determine the signal quality, the response from the tag is detected by the "main" (pin RX_IN1) and "auxiliary" (pin RX_IN2) RSSI. Both values measured and stored in the RSSI Levels and Oscillator Status register (address 0x0F). The MCU can read the RSSI values from the TRF7964A RSSI register and make the decision if swapping the input- signals is preferable or not. Setting B3 in Chip Status Control register (address 0x00) to 1 connects RX_IN1 (pin 8) to the auxiliary received and RX_IN2 (pin 9) to the main receiver.

The main and auxiliary receiver input stages are RF envelope detectors. The RF amplitude at RX_IN1 and RX_IN2 should be approximately 3 VPP for a V_INsupply level greater than 3.3 V. If the V_IN level is lower, the RF input peak-to-peak voltage level should not exceed the V_INlevel.

6.4.2 Receiver Gain and Filter Stages

The first gain and filtering stage has a nominal gain of 15 dB with an adjustable band-pass filter. The band-pass filter has programmable 3-dB corner frequencies between 110 kHz to 450 kHz for the high-pass filter and 570 kHz to 1500 kHz for the low-pass filter. After the band-pass filter, there is another gain-and-filtering stage with a nominal gain of 8 dB and with frequency characteristics identical to the first band-pass stage.

The internal filters are configured automatically depending on the selected ISO communication standard in the ISO Control register (address 0x01). If required, additional fine tuning can be done by writing directly to the RX Special Setting registers (address 0x0A).

Table 6-5 shows the various settings for the receiver analog section. Setting B4, B5, B6, and B7 to 0 results in a band-pass characteristic of 240 kHz to 1.4 MHz, which is appropriate for ISO/IEC 14443 B 106 kbps, ISO/IEC 14443 A and B data rates of 212 kbps and 424 kbps, and FeliCa 424 kbps.

Table 6-6 Coding of the ISO Control Register

Table 6-7 Coding of the ISO Control Register For RFID Mode (B5 = 0)

6.5.1 Received Signal Strength Indicator (RSSI)

The TRF7964A incorporates in total three independent RSSI building blocks: Internal Main RSSI, Internal Auxiliary RSSI, and External RSSI. The internal RSSI blocks measure the amplitude of the subcarrier signal, and the external RSSI block measures the amplitude of the RF carrier signal at the receiver input.

6.5.1.1 Internal RSSI – Main and Auxiliary Receivers

Each receiver path has its own RSSI block to measure the envelope of the demodulated RF signal (subcarrier). Internal Main RSSI and Internal Auxiliary RSSI are identical however connected to different RF input pins. The Internal RSSI is intended for diagnostic purposes to set the correct RX path conditions.

The internal RSSI values can be used to adjust the RX gain settings or determine which RX path (main or auxiliary) provides the greater amplitude and, hence, to determine if the MUX may need to be reprogrammed to swap the RX input signal. The measuring system latches the peak value, so the RSSI level can be read after the end of each receive packet. The RSSI register values are reset with every transmission (TX) by the reader. This ensures an updated RSSI measurement for each new tag response.

The Internal RSSI has 7 steps (3 bit) with a typical increment of approximately 4 dB. The operating range is between 600 mV_PP and 4.2 V_PP with a typical step size of approximately 600 mV. Both Internal Main and Internal Auxiliary RSSI values are stored in the RSSI Levels and Oscillator Status register (0x0F). The nominal relationship between the input RF peak level and the RSSI value is shown in Figure 6-5.

Figure 6-5 Digital Internal RSSI (Main and Auxiliary) Value vs RF Input Level in V_PP (V)

This RSSI measurement is done during the communication to the Tag; this means the TX must be on. Bit 1 in the Chip Status Control register (0x00) defines if Internal RSSI or the External RSSI value is stored in the RSSI Levels and Oscillator Status register (0x0F). Direct command 0x18 is used to trigger an Internal RSSI measurement.

6.5.1.2 External RSSI

The external RSSI is mainly used to check for any external 13.56-MHz signals at the receiver RX_IN1 input. The external RSSI measurement should be used before turning on the transmitter to prevent RF field collisions. This is especially important for active mode, when both devices emit their own RF field. The level of the RF signal received at the antenna is measured and stored in the RSSI Levels and Oscillator Status register (0x0F). Figure 6-6 shows the relationship between the voltage at the RX_IN1 input and the 3-bit code.

Figure 6-6 Digital External RSSI Value vs RF Input Level in V_PP (mV)

The relation between the 3-bit code and the external RF field strength (A/m) sensed by the antenna must be determined by calculation or by experiments for each antenna design. The antenna Q-factor and connection to the RF input influence the result. Direct command 0x19 is used to trigger an external RSSI measurement.

For clarity, to check the internal or external RSSI value independent of any other operation, the user must:

1. Set transmitter to desired state (on or off) using Bit 5 of Chip Status Control register (0x00) and enable receiver using Bit 1.
2. Check internal or external RSSI using direct commands 0x18 or 0x19, respectively. This action places the RSSI value in the RSSI register.
3. Delay at least 50 µs.
4. Read the RSSI register using direct command 0x0F; values range from 0x40 to 0x7F.
5. Repeat steps 1 to 4 as needed. The register is reset when it is read.

Table 6-8 Minimum Crystal Recommendations

6.10.1 General Introduction

The communication interface to the reader can be configured in two ways: with a eight line parallel interface (D0:D7) plus DATA_CLK, or with a 4-wire Serial Peripheral Interface (SPI). The SPI interface uses traditional Master Out/Slave In (MOSI), Master In/Slave Out (MISO), Slave Select, and DATA_CLK lines.

These communication modes are mutually exclusive; that is, only one mode can be used at a time in the application.

When the SPI interface is selected, the unused I/O_2, I/O_1, and I/O_0 pins must be hard-wired as shown in Table 6-9. At power up, the TRF7964A samples the status of these three pins and then enters one of the possible SPI modes.

The TRF7964A always behaves as the slave device, and the microcontroller (MCU) behaves as the master device. The MCU initiates all communications with the TRF7964A, and the TRF7964A makes use of the Interrupt Request (IRQ) pin in both parallel and SPI modes to prompt the MCU for servicing attention.

Communication is initialized by a start condition, which is expected to be followed by an Address/Command word (Adr/Cmd). The Adr/Cmd word is 8 bits long, and Table 6-10 shows its format.

The MSB (bit 7) determines if the word is to be used as a command or as an address. The last two columns of Table 6-10 show the function of the separate bits if either address or command is written. Data is expected once the address word is sent. In continuous-address mode (Cont. mode = 1), the first data that follows the address is written (or read) to (from) the given address. For each additional data, the address is incremented by one. Continuous mode can be used to write to a block of control registers in a single stream without changing the address; for example, setup of the predefined standard control registers from the MCU nonvolatile memory to the reader. In noncontinuous address mode (simple addressed mode), only one data word is expected after the address.

Address Mode is used to write or read the configuration registers or the FIFO. When writing more than 12 bytes to the FIFO, the Continuous Address Mode should be set to 1.

Command Mode is used to enter a command resulting in reader action (for example, initialize transmission, enable reader, and turn reader on or off).

The following sections give examples of the expected communications between an MCU and the TRF7964A.

6.10.1.1 Continuous Address Mode

Figure 6-8 summarizes the continuous address mode communication. Figure 6-8 and Figure 6-9 show the signals between the MCU and the TRF7964A.

Table 6-11 Continuous Address Mode

Start

Adr x

Data(x)

Data(x+1)

Data(x+2)

Data(x+3)

Data(x+4)

...

Data(x+n)

StopCont

Figure 6-8 Continuous Address Register Write Example Starting With Register 0x00 Using SPI With SS

Figure 6-9 Continuous Address Register Read Example Starting With Register 0x00 Using SPI With SS

6.10.1.2 Noncontinuous Address Mode (Single Address Mode)

Table 6-12 summarizes the noncontinuous address (single address) mode communication. Figure 6-10 and Figure 6-11 show the signals between the MCU and the TRF7964A.

Table 6-12 Noncontinuous Address Mode (Single Address Mode)

Start

Adr x

Data(x)

Adr y

Data(y)

...

Adr z

Data(z)

StopSgl

Figure 6-10 Single Address Register Write Example of Register 0x00 Using SPI With SS

Figure 6-11 Single Address Register Read Example of Register 0x00 Using SPI With SS

6.10.1.3 Direct Command Mode

Table 6-13 summarizes the direct command mode communication. Figure 6-12 shows the signals between the MCU and the TRF7964A.

Table 6-13 Direct Command Mode

Start

Cmd x

(Optional data or command)

Stop

Figure 6-12 Direct Command Example of Sending 0x0F (Reset) Using SPI With SS

Section 6.13 describes the other direct command codes from the MCU to the TRF7964A IC.

6.10.1.4 FIFO Operation

The FIFO is a 127-byte register at address 0x1F with byte storage locations 0 to 126. FIFO data is loaded in a cyclical manner and can be cleared by a reset command (0x0F) (see Figure 6-12 showing this direct command).

Associated with the FIFO are two counters and three FIFO status flags. The first counter is a 7-bit FIFO byte counter (bits B0 to B6 in register 0x1C) that tracks the number of bytes loaded into the FIFO. If the number of bytes in the FIFO is n, the register value is n (number of bytes in FIFO register). For example, if 8 bytes are in the FIFO, the FIFO counter (Register 0x1C) has the hexadecimal value of 0x08 (binary value of 00001000).

A second counter (12 bits wide) indicates the number of bytes being transmitted (registers 0x1D and 0x1E) in a data frame. An extension to the transmission-byte counter is a 4-bit broken-byte counter also provided in register 0x1E (bits B0 to B3). Together these counters make up the TX length value that determines when the reader generates the EOF byte.

During transmission, the FIFO is checked for an almost-empty condition, and during reception for an almost-full condition. The maximum number of bytes that can be loaded into the FIFO in a single sequence is 127 bytes.

NOTE

The number of bytes in a frame, transmitted or received, can be greater than 127 bytes.

During transmission, the MCU loads the TRF7964A FIFO (or during reception the MCU removes data from the FIFO), and the FIFO counter counts the number of bytes being loaded into the FIFO. Meanwhile, the byte counter keeps track of the number of bytes being transmitted. An interrupt request is generated if the number of bytes in the FIFO triggers the watermark levels, which are configured in the Adjustable FIFO IRQ Levels register (0x14). The default setting is for the interrupt to be triggered when receiving 124 bytes during RX or having 4 bytes remaining during TX. These watermark levels are used so that MCU can send new data or read the data as necessary. The MCU must also validate the number of data bytes to be sent, so as to not surpass the value defined in the TX Length Byte registers (0x1D and 0x1E). The MCU also signals the transmit logic when the last byte of data is sent or was removed from the FIFO during reception.

Figure 6-13 shows an example of checking the FIFO Status register using SPI with SS.

Figure 6-13 Example of Checking the FIFO Status Register Using SPI With SS

6.10.2 Parallel Interface Mode

In parallel mode, the start condition is generated on the rising edge of the I/O_7 pin while the CLK is high.

This is used to reset the interface logic. Figure 6-14, Figure 6-15, and Figure 6-16 show the sequence of the data, with an 8-bit address word first, followed by data.

Communication is ended by:

• The StopSmpl condition, where a falling edge on the I/O_7 pin is expected while CLK is high.
• The StopCont condition, where the I/O_7 pin must have a successive rising and falling edge while CLK is low to reset the parallel interface and be ready for the new communication sequence.
• The StopSmpl condition is also used to terminate the direct mode.

Figure 6-14 Parallel Interface Communication With Simple Stop Condition (StopSmpl)

Figure 6-15 Parallel Interface Communication With Continuous Stop Condition (StopCont)

Figure 6-16 Example of Parallel Interface Communication With Continuous Stop Condition

6.10.3 Reception of Air Interface Data

At the start of a receive operation (when SOF is successfully detected), B6 is set in the IRQ Status register. An RX complete interrupt request is sent to the MCU at the end of the receive operation if the receive data string is shorter than or equal to the number of bytes configured in the Adjustable FIFO IRQ Levels register (0x14). An IRQ_FIFO interrupt request is sent to the MCU during the receive operation if the data string is greater than the level set in the Adjustable FIFO IRQ Levels register (0x14). After receiving an IRQ_FIFO or RX complete interrupt, the MCU must read the FIFO Status register (0x1C) to determine the number of bytes to be read from the FIFO. Next, the MCU must read the data in the FIFO. It is optional but recommended to read the FIFO Status register (0x1C) after reading FIFO data to determine if the receive is complete. In the case of an IRQ_FIFO, the MCU should expect either another IRQ_FIFO or RX complete interrupt. This is repeated until an RX complete interrupt is generated. The MCU receives the interrupt request, then checks to determine the reason for the interrupt by reading the IRQ Status register (0x0C), after which the MCU reads the data from the FIFO.

If the reader detects a receive error, the corresponding error flag is set (framing error, CRC error) in the IRQ Status register, indicating to the MCU that reception was not completed correctly.

6.10.4 Data Transmission From MCU to TRF7964A

Before beginning data transmission, the FIFO should always be cleared with a reset command (0x0F). Data transmission is initiated with a selected command (see Section 6.13). The MCU then commands the reader to do a continuous write command (0x3D) starting from register 0x1D. Data written into register 0x1D is the TX Length Byte 1 (upper and middle nibbles), while the following byte in register 0x1E is the TX Length Byte 2 (lower nibble and broken byte length) (see Table 6-47 and Table 6-48) . Note that the TX byte length determines when the reader sends the end of frame (EOF) byte. After the TX length bytes are written, FIFO data is loaded in register 0x1F with byte storage locations 0 to 127. Data transmission begins automatically after the first byte is written into the FIFO. The loading of TX length bytes and the FIFO can be done with a continuous-write command, as the addresses are sequential.

At the start of transmission, the flag B7 (IRQ_TX) is set in the IRQ Status register, and at the end of the transmit operation, an interrupt is sent to inform the MCU that the task is complete.

6.10.5 Serial Interface Communication (SPI)

When an SPI interface is used, I/O pins I/O_2, I/O_1, and I/O_0 must be hard wired according to Table 6-9. On power up, the TRF7964A looks for the status of these pins and then enters into the corresponding mode.

The serial communications work in the same manner as the parallel communications with respect to the FIFO, except for the following condition. On receiving an IRQ from the reader, the MCU reads the TRF7964A IRQ Status register to determine how to service the reader. After this, the MCU must to do a dummy read to clear the reader's IRQ status register. The dummy read is required in SPI mode because the reader's IRQ status register needs an additional clock cycle to clear the register. This is not required in parallel mode because the additional clock cycle is included in the Stop condition. When first establishing communications with the TRF7964A, the SOFT_INIT (0x03) and IDLE (0x00) commands should be sent first from the MCU (see Table 6-14).

The procedure for a dummy read is as follows (see Figure 6-17 and Figure 6-18):

1. Start the dummy read:
   1. When using slave select (SS): set SS bit low.
   2. When not using SS: start condition is when Data Clock is high (see Table 6-9).
2. Send address word to IRQ status register (0x0C) with read and continuous address mode bits set to 1 (see Table 6-9).
3. Read 1 byte (8 bits) from IRQ status register (0x0C).
4. Dummy-read 1 byte from register 0x0D (collision position and interrupt mask).
5. Stop the dummy read:
   1. When using slave select (SS): set SS bit high.
   2. When not using SS: stop condition when Data Clock is high.

Figure 6-17 Procedure for Dummy Read

Figure 6-18 Example of Dummy Read Using SPI With SS

6.10.5.1 Serial Interface Mode With Slave Select (SS)

The serial interface is in reset while the Slave Select signal is high. Serial data in (MOSI) changes on the rising edge, and is validated in the reader on the falling edge, as shown in Figure 6-19. Communication is terminated when the Slave Select signal goes high.

All words must be 8 bits long with the MSB transmitted first.

Figure 6-19 SPI With Slave Select Timing Diagram

The read command is sent out on the MOSI pin, MSB first, in the first eight clock cycles. MOSI data changes on the rising edge, and is validated in the reader on the falling edge, as shown in Figure 6-19. During the write cycle, the serial data out (MISO) is not valid. After the last read command bit (B0) is validated at the eighth falling edge of SCLK, valid data can be read on the MISO pin at the falling edge of SCLK. It takes eight clock edges to read out the full byte (MSB first). See Section 5.4 for electrical specifications related to Figure 6-19.

Figure 6-20 and Figure 6-21 show the continuous read operation.

Figure 6-20 Continuous Read Operation Using SPI With Slave Select

Figure 6-21 Continuous Read of Registers 0x00 to 0x05 Using SPI With SS

Figure 6-22 shows an example of performing a single slot inventory command. Reader registers (in this example) are configured for 5 VDC in and default operation.

Figure 6-22 Inventory Command Sent From MCU to TRF7964A

The TRF7964A takes these bytes from the MCU and then send out Request Flags, Inventory Command, and Mask over the air to the ISO/IEC 15693 transponder. After these three bytes have been transmitted, an interrupt occurs to indicate back to the reader that the transmission has been completed. In the example in Figure 6-23, this IRQ occurs approximately 1.6 ms after the SS line goes high after the Inventory command is sent out.

Figure 6-23 IRQ After Inventory Command

The IRQ status register read (0x6C) yields 0x80, which indicates that TX is indeed complete. This is followed by a dummy clock. Then, if a tag is in the field and no error is detected by the reader, a second interrupt is expected and occurs (in this example) approximately 4 ms after first IRQ is read and cleared.

In the continuation of the example (see Figure 6-24), the IRQ Status Register is read using method previously recommended, followed by a single read of the FIFO Status register, which indicates that there are 10 bytes to be read out.

Figure 6-24 Read IRQ Status Register After Inventory Command

This is then followed by a continuous read of the FIFO (see Figure 6-25). The first byte is (and should be) 0x00 for no error. The next byte is the DSFID (usually shipped by manufacturer as 0x00), then the UID, shown here up to the next most significant byte, the MFG code [shown as 0x07 (TI silicon)].

Figure 6-25 Continuous Read of FIFO After Inventory Command

TI recommends resetting the FIFO after receiving data. Additionally, the RSSI value of the tag can be read out at this point. In the example in Figure 6-26, the transponder is very close to the antenna, so value of 0x7F is recovered.

Figure 6-26 Reset FIFO and Read RSSI

6.10.6 Direct Mode

Direct mode allows the user to configure the reader in one of two ways. Direct mode 0 (bit 6 = 0, as defined in ISO Control register) allows the user to use only the front-end functions of the reader, bypassing the protocol implementation in the reader. For transmit functions, the user has direct access to the transmit modulator through the MOD pin (pin 14). On the receive side, the user has direct access to the subcarrier signal (digitized RF envelope signal) on I/O_6 (pin 23).

Direct mode 1 (bit 6 = 1, as defined in ISO Control register) uses the subcarrier signal decoder of the selected protocol (as defined in ISO Control register). This means that the receive output is not the subcarrier signal but the decoded serial bit stream and bit clock signals. The serial data is available on I/O_6 (pin 23) and the bit clock is available on I/O_5 (pin 22). The transmit side is identical; the user has direct control over the RF modulation through the MOD input. This mode is provided so that the user can implement a protocol that has the same bit coding as one of the protocols implemented in the reader, but needs a different framing format.

To select direct mode, the user must first choose which direct mode to enter by writing B6 in the ISO Control register. This bit determines if the receive output is the direct subcarrier signal (B6 = 0) or the serial data of the selected decoder. If B6 = 1, then the user must also define which protocol should be used for bit decoding by writing the appropriate setting in the ISO Control register.

The reader actually enters the direct mode when B6 (direct) is set to 1 in the chip status control register. Direct mode starts immediately. The write command should not be terminated with a stop condition (see communication protocol), because the stop condition terminates the direct mode and clears B6. This is necessary as the direct mode uses one or two I/O pins (I/O_6, I/O_5). Normal parallel communication is not possible in direct mode. Sending a stop condition terminates direct mode.

Figure 6-27 shows the different configurations available in direct mode.

• In mode 0, the reader is used as an AFE only, and protocol handling is bypassed.
• In mode 1, framing is not done, but SOF and EOF are present. This allows for a user-selectable framing level based on an existing ISO standard.
• In mode 2, data is ISO-standard formatted. SOF, EOF, and error checking are removed, so the microprocessor receives only bytes of raw data through a 127-byte FIFO.

Figure 6-27 User-Configurable Modes

The steps to enter direct mode are listed below, using SPI with SS communication method only as one example, as direct modes are also possible with parallel and SPI without SS. The must enter direct mode 0 to accommodate card type communications that are not compliant with ISO standards. Direct mode can be entered at any time, so if a card type started with ISO standard communications, then deviated from the standard after being identified and selected, the ability to go into direct mode 0 is very useful.

Step 1: Configure Pins I/O_0 to I/O_2 for SPI with SS

Step 2: Set Pin 12 of the TRF7964A (ASK/OOK pin) to 0 for ASK or 1 for OOK

Step 3: Program the TRF7964A registers

The following registers must be explicitly set before going into the direct mode.

1. ISO Control register (0x01) to the appropriate standard
   • 0x02 for ISO/IEC 15693 High Data Rate
   • 0x08 for ISO/IEC 14443 A (106 kbps)
   • 0x1A for FeliCa 212 kbps
   • 0x1B for FeliCa 424 kbps
2. Modulator and SYS_CLK register (0x09) to the appropriate clock speed and modulation
   • 0x21 for 6.78 MHz Clock and OOK (100%) modulation
   • 0x20 for 6.78 MHz Clock and ASK 10% modulation
   • 0x22 for 6.78 MHz Clock and ASK 7% modulation
   • 0x23 for 6.78 MHz Clock and ASK 8.5% modulation
   • 0x24 for 6.78 MHz Clock and ASK 13% modulation
   • 0x25 for 6.78 MHz Clock and ASK 16% modulation
     (See register 0x09 definition for all other possible values)

Example register setting for ISO/IEC 14443 A at 106 kbps:

• ISO Control register (0x01) to 0x08
• RX No Response Wait Time register (0x07) to 0x0E
• RX Wait Time register (0x08) to 0x07
• Modulator control register (0x09) to 0x21 (or any custom modulation)
• RX Special Settings register (0x0A) to 0x20

Step 4: Entering Direct Mode 0

The following registers must be programmed to enter direct mode 0:

1. Set bit B6 of the Modulator and SYS_CLK Control register (0x09) to 1.
2. Set bit B6 of the ISO Control (Register 01) to 0 for direct mode 0 (default its 0)
3. Set bit B6 of the Chip Status Control register (0x00) to 1 to enter direct mode
4. Send extra eight clock cycles (see Figure 6-28, this step is TRF7964A specific)

NOTE

• It is important that the last write is not terminated with a stop condition. For SPI, this means that Slave Select (I/O_4) stays low.
• Sending a Stop condition terminates the direct mode and clears bit B6 in the Chip Status Control register (0x00).

The reader enters the direct mode 0 when bit 6 of the Chip Status Control register (0x00) is set to a 1 and stays in direct mode 0 until a stop condition is sent from the microcontroller.

Figure 6-28 Entering Direct Mode 0

Step 5: Transmit Data Using Direct Mode

The application now has direct control over the RF modulation through the MOD input (see Figure 6-29).

Figure 6-29 Direct Control Signals

The microcontroller is responsible for generating data according to the coding specified by the particular standard. The microcontroller must generate SOF, EOF, Data, and CRC. In direct mode, the FIFO is not used and no IRQs are generated. See the applicable ISO standard to understand bit and frame definitions. Figure 6-30 shows an example of what the developer sees when using DM0 in an actual application. This figure clearly shows the relationship between the MOD pin being controlled by the MCU and the resulting modulated 13.56-MHz carrier signal.

Figure 6-30 TX Sequence Out in DM0

Step 6: Receive Data Using Direct Mode

After the TX operation is complete, the tag responds to the request and the subcarrier data is available on pin I/O_6. The microcontroller needs to decode the subcarrier signal according to the standard. This includes decoding the SOF, data bits, CRC, and EOF. The CRC then needs to be checked to verify data integrity. The receive data bytes must be buffered locally.

As an example of the receive data bits and framing level according to the ISO/IEC 14443 A standard is shown in Figure 6-31 (taken from ISO/IEC 14443 specification and TRF7964A air interface).

Figure 6-31 Receive Data Bits and Framing Level

Figure 6-32 shows an example of what the developer should expect on the I/O_6 line during the RX process while in direct mode 0.

Figure 6-32 RX Sequence on I/O_6 in DM0 (Analog Capture)

Step 7: Terminating Direct Mode 0

After the EOF is received, data transmission is over, and direct mode 0 can be terminated by sending a Stop Condition (in the case of SPI, make the Slave Select go high). The TRF7964A is returned to default state.

6.13.1 Command Codes

Table 6-14 summarizes the command codes.

The command code values from Table 6-14 are substituted in Table 6-15, bits 0 through 4. Also, the most-significant bit (MSB) in Table 6-15 must be set to 1. (Table 6-15 is same as Table 6-10, shown here again for easy reference).

The MSB determines if the word is to be used as a command or address. The last two columns of Table 6-15 show the function of each bit, depending on whether address or command is written. Command mode is used to enter a command resulting in reader action (initialize transmission, enable reader, and turn reader on or off).

6.14.1 Register Preset

After power up and the EN pin low-to-high transition, the reader is in the default mode. The default configuration is ISO/IEC 15693, single subcarrier, high data rate, 1-out-of-4 operation. The low-level option registers (0x02 to 0x0B) are automatically set to adapt the circuitry optimally to the appropriate protocol parameters. When entering another protocol (by writing to the ISO Control register 0x01), the low-level option registers (0x02 to 0x0B) are automatically configured to the new protocol parameters. After selecting the protocol, it is possible to change some low-level register contents if needed. However, changing to another protocol and then back, reloads the default settings, and so then the custom settings must be reloaded.

The Clo0 and Clo1 register (0x09) bits, which define the microcontroller frequency available on the SYS_CLK pin, are the only 2 bits in the configuration registers that are not cleared during protocol selection.

6.14.2 Register Overview

Table 6-19 lists the registers.

6.14.3 Detailed Register Description