ZHCSHL5C February 2018 – September 2019 TS3USBCA4
PRODUCTION DATA.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
I2C | ||||||
fSCL | I2C clock frequency | 400 | kHz | |||
tBUF | Bus free time between START and STOP conditions | 1.3 | µs | |||
tHDSTA | Hold time after repeated START condition. After this period, the first clock pulse is generated | 0.6 | µs | |||
tLOW | Low period of the I2C clock | 1.3 | µs | |||
tHIGH | High period of the I2C clock | 0.6 | µs | |||
tSUSTA | Setup time for a repeated START condition | 0.6 | µs | |||
tHDDAT | Data hold time | 0 | µs | |||
tSUDAT | Data setup time | 150 | ns | |||
tR | Rise time of both SDA and SCL signals | 300 | ns | |||
tF | Fall time of both SDA and SCL signals | 20 × (VI2C/5.5 V) | 300 | ns | ||
tSUSTO | Setup time for STOP condition | 0.6 | µs |