8.5 Programming

The TS3USBCA4 can be controlled using I²C. The SCL and SDA terminals are used for I²C clock and I²C data respectively.

The following procedure should be followed to write to TS3USBCA4 I²C registers:

1. The master initiates a write operation by generating a start condition (S), followed by the TS3USBCA4 7-bit address and a zero-value “W/R” bit to indicate a write cycle
2. The TS3USBCA4 acknowledges the address cycle.
3. The master presents the sub-address (I²C register within TS3USBCA4) to be written, consisting of one byte of data, MSB-first.
4. The TS3USBCA4 acknowledges the sub-address cycle.
5. The master presents the first byte of data to be written to the I²C register.
6. The TS3USBCA4 acknowledges the byte transfer.
7. The master may continue presenting additional bytes of data to be written, with each byte transfer completing with an acknowledge from the TS3USBCA4.
8. The master terminates the write operation by generating a stop condition (P).

The following procedure should be followed to read the TS3USBCA4 I²C registers:

1. The master initiates a read operation by generating a start condition (S), followed by the TS3USBCA4 7-bit address and a one-value “W/R” bit to indicate a read cycle
2. The TS3USBCA4 acknowledges the address cycle.
3. The TS3USBCA4 transmit the contents of the memory registers MSB-first starting at register 00h or last read sub-address+1. If a write to the I²C.register occurred prior to the read, then the TS3USBCA4 shall start at the sub-address specified in the write.
4. The TS3USBCA4 shall wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the master after each byte transfer; the I²C master acknowledges reception of each data byte transfer.
5. If an ACK is received, the TS3USBCA4 transmits the next byte of data.
6. The master terminates the read operation by generating a stop condition (P).

The following procedure should be followed for setting a starting sub-address for I²C reads:

1. The master initiates a write operation by generating a start condition (S), followed by the TS3USBCA4 7-bit address and a zero-value “W/R” bit to indicate a write cycle.
2. The TS3USBCA4 acknowledges the address cycle.
3. The master presents the sub-address (I²C register within TS3USBCA4) to be written, consisting of one byte of data, MSB-first.
4. The TS3USBCA4 acknowledges the sub-address cycle.
5. The master terminates the write operation by generating a stop condition (P).