9.2.2 Detailed Design Procedure

The design procedure starts with the choice of supply. TS3USBCA4 wide supply range from 2.4 V to 5.5 V gives the designer flexibility when selecting a supply. Examples include, but are not limited to, a single-cell battery, a 3.3-V regulator, or VBUS. The designer must account for the parametric variation of TS3USBCA4 with supply range, the supply range of other components in the system, the IO voltage levels of companion devices, and cost. For example, a regulated 3.3-V V_CC has the advantage of smaller variation of TS3USBCA4 performance compared to a single-cell batter between 2.7 V and 4.3 V. This regulator may add to the system cost and board area.

The next step in the design procedure is to choose between I²C- and pin-configuration mode. The I²C-configuration mode is preferred because it reduces the number of IOs needed from the micro-processor. Note that in TS3USBCA420 the flip functionality is only available in the I²C-configuration mode. The designer can choose from two I²C slave addresses through pin-strapping of I2C_EN to avoid address conflict. The IOs of TS3USBCA4 have well-controlled V_IH and V_IL and are supposed to work with a wide range of IO voltage levels of the micro-processor. However, the designer needs to check the compatibility of the IOs between the micro-processor and TS3USBCA4, and insert level translators when necessary.

In I²C-configuration mode, when it is necessary to set I2C_EN to the middle level to avoid slave address conflict, it is desirable to use as high a resistor value as possible for the resistor divider to minimize the static current through the resistor divider. However, the designer needs to take into account the resistor tolerance and the effect of the on-chip pull-down resistor to ensure a satisfactory voltage margin for V_IM of the I2C_EN pin.

It should be noted that the bandwidth of the high-speed lanes is defined with the audio channel open. Due to the low R_ON of the audio channel, big parasitic capacitance exists between the audio output port and the SBU port. The load (capacitive and/or resistive) at the audio output port may significantly impact the bandwidth of the high-speed lanes. If bandwidth is importance, the audio channel is preferred. If certain high-speed signals have to go through the high-speed lanes, care should be taken to minimize the load at the audio output port, including the traces.