ZHCSHG2E January   2018  – April 2019 TS5MP646

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      D-PHY 简化原理图
      2.      C-PHY 简化原理图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Powered-Off Protection
      2. 8.3.2 1.8-V Logic Compatible Inputs
      3. 8.3.3 Low Power Disable Mode
    4. 8.4 Device Functional Modes
      1. 8.4.1 Pin Functions
      2. 8.4.2 Low Power Disable Mode
      3. 8.4.3 Switch Enabled Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
        1. 9.2.3.1 MIPI D-PHY Application
        2. 9.2.3.2 MIPI C-PHY Application
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 文档支持
    2. 12.2 接收文档更新通知
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 术语表
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY
IDD VDD Active Supply Current VDD = 1.65 V to 5.5 V
OE = 0 V
SEL = 0 V to 5.5 V
Dn, CLKn = 0 V		 0 30 60 µA
IDD_PD Power-down Supply current VDD = 1.65 V to 5.5 V
OE = VDD
SEL = 0 V to 5.5 V
Dn, CLKn = 0 V		 0 0.1 1 µA
IDD_PD_1.8 Power-down Supply current VDD = 1.65 V to 5.5 V
OE = 1.8 V
SEL = 0 V to 5.5 V
Dn, CLKn = 0 V		 0 0.1 10 µA
DC CHARACTERISTICS
RON_HS On-state resistance VDD = 1.65 V to 5.5 V
OE = 0 V
Dn, CLKn = -8 mA, 0.2 V
DAn, DBn, CLKAn, CLKBn = 0.2 V, -8 mA		 6 9 Ω
RON_LP On-state resistance VDD = 1.65 V to 5.5 V
OE = 0 V
Dn, CLKn = -8 mA, 1.2 V
DAn, DBn, CLKAn, CLKBn = 1.2 V, -8 mA		 6 10 Ω
RON_flat_HS On-state resistance flatness VDD = 1.65 V to 5.5 V
OE = 0 V
Dn, CLKn = -8 mA, 0 V to 0.3 V
DAn, DBn, CLKAn, CLKBn = 0 V to 0.3 V, -8 mA		 0.1 Ω
RON_flat_LP On-state resistance flatness VDD = 1.65 V to 5.5 V
OE = 0 V
Dn, CLKn = -8 mA, 0 V to 1.3 V
DAn, DBn, CLKAn, CLKBn = 0 V to 1.3 V, -8 mA		 0.9 Ω
DRON_HS On-state resistance match between+and - paths VDD = 1.65 V to 5.5 V
OE = 0 V
Dn, CLKn = -8 mA, 0.2 V
DAn, DBn, CLKAn, CLKBn = 0.2 V, -8 mA		 0.1 Ω
DRON_LP On-state resistance match between+and - paths VDD = 1.65 V to 5.5 V
OE = 0 V
Dn, CLKn = -8 mA, 1.3 V
DAn, DBn, CLKAn, CLKBn = 1.3 V, -8 mA		 0.1 Ω
IOFF Switch off leakage current VDD = 1.65 V to 5.5 V
OE = 0 V to 5.5 V
SEL = 0 V to 5.5 V
Dn, CLKn = 0 V to 1.3 V
DAn, DBn, CLKAn, CLKBn = 0 V to 1.3 V		 -0.5 0.5 µA
IOFF_3_6 Switch off leakage current VDD = 0V1.5V,1.65V,3.3V,5.5V
/OE = 0V,1.5V,1.65V,3.3V,5.5V
SEL= 0V,1.5V,1.65V,3.3V,5.5V
DX,CLKX = 3.6V
DAX,DBx,CLKAX,CLKBX = 3.6V		 -10 10 µA
ION Switch on leakage current VDD = 1.65 V to 5.5 V
OE = 0 V
SEL = 0 V to 5.5 V
Dn, CLKn = 0 V to 1.3 V
DAn, DBn, CLKAn, CLKBn = 0 V to 1.3 V		 -0.5   0.5 µA
ION_3_6 Switch on leakage current VDD = 1.5V,1.65V,3.3V,5.5V
/OE = 0V
SEL= 0V,1.5V,1.65V,3.3V,5.5V
DX,CLKX = 3.6V
DAX,DBx,CLKAX,CLKBX = 3.6V		 -50 50 µA
DYNAMIC CHARACTERISTICS
tSWITCH Switching time between channels VDD = 1.65 V to 5.5 V
OE = 0 V
Dn, CLKn = 0.6 V
DAn, DBn, CLKAn, CLKBn:  RL = 50 Ω, CL = 1 pF		 1.5 µs
tSWITCH_CP Switching time between channels by charge pump VDD = 1.5V,1.65V,3.3V,5.5V
/OE = 0V
DX, CLKX = 0.6 V
DAX, DBX, CLKAX, CLKBX:  RL=50Ω,CL=5pF		     50 µs
fSEL_MAX Maximum toggling frequency for the SEL line VDD = 1.65 V to 5.5 V
Dn, CLKn = 0.6 V
DAn, DBn, CLKAn, CLKBn:  RL = 50 Ω, CL = 1 pF		 100 kHz
tON_OE Device turnon-time OE to switch on VDD = 1.65 V to 5.5 V
Dn, CLKn = 0.6 V
DAn, DBn, CLKAn, CLKBn:  RL = 50 Ω, CL = 1 pF		 50 300 µs
tON_VDD Device turnon-time VDD to switch on VDD = 0 V to 5.5 V
Dn, CLKn = 0.6 V
DAn, DBn, CLKAn, CLKBn:  RL = 50 Ω, CL = 1 pF		 50 300 µs
tOFF_OE Device turnoff time OE to switch off VDD = 1.65 V to 5.5 V
Dn, CLKn = 0.6 V
DAn, DBn, CLKAn, CLKBn:  RL = 50 Ω, CL = 1 pF		 0.5 1 µs
tOFF_VDD Device turnoff time VDD to switch off VDD = 5 V to 0 V
VDD ramp rate = 250 µs
Dn, CLKn = 0.6 V
DAn, DBn, CLKAn, CLKBn:  RL = 50 Ω, CL = 1 pF		 0.5 1 ms
tMIN_/OE Minimum pulse width for OE VDD = 1.65 V to 5.5 V
Dn, CLKn = 0.6 V
DAn, DBn, CLKAn, CLKBn:  RL = 50 Ω, CL = 1 pF		 500 ns
tBBM Break before make time VDD = 1.65 V to 5.5 V
OE = 0 V
Dn, CLKn = RL = 50 Ω, CL = 1 pF
DAn, DBn, CLKAn, CLKBn:  0.6 V		 50 ns
tSKEW Intrapair skew VDD = 1.65 V to 5.5 V
OE = 0 V
Dn, CLKn = 0.3 V
DnX, DBn, CLKAn, CLKBn:  RL = 50 Ω, CL = 1 pF		 1 ps
tSKEW Interpair Skew VDD = 1.65 V to 5.5 V
OE = 0 V
Dn, CLKn = 0.3 V
DAn, DBn, CLKAn, CLKBn:  RL = 50 Ω, CL = 1 pF		 4 ps
tPD Propagation delay with 100 ps rise time VDD = 1.65 V to 5.5 V
OE = 0 V
Dn, CLKn = 0.6 V
DAn, DBn, CLKAn, CLKBn:  RL = 50 Ω, CL = 1 pF
tRISE = 100 ps		 40 ps
OISO Differential off isolation VDD = 1.65 V to 5.5 V
OE = 0 V, VDD
SEL = 0 V, VDD
Dn, CLKn, DAn, DBn, CLKAn, CLKBn: RS = 50 Ω, RL = 50 Ω, CL = 1 pF
VI/O = 200 mV+200 mVPP (differential)
f = 1250 MHz		 -20 dB
XTALK Differential channel to channel crosstalk VDD = 1.65 V to 5.5 V
OE = 0 V, VDD
SEL = 0 V, VDD
Dn, CLKn, DAn, DBn, CLKAn, CLKBn: RS = 50 Ω, RL = 50 Ω, CL = 1 pF
VI/O = 200 mV+200 mVPP (differential)
f = 1250 MHz		 -40 dB
BW Differential Bandwidth
 		 VDD = 1.65 V to 5.5 V
OE = 0 V
SEL = 0 V, VDD
Dn, CLKn, DAn, DBn, CLKAn, CLKBn: RS = 50 Ω, RL = 50 Ω, CL = 1 pF
VI/O = 200 mV+200 mVPP (differential)
f = 1250 MHz		 2.7 4.1 GHz
ILOSS Insertion Loss VDD = 1.65 V to 5.5 V
OE = 0 V
SEL = 0 V, VDD
Dn, CLKn, DAn, DBn, CLKAn, CLKBn: RS = 50 Ω, RL = 50 Ω, CL = 1 pF
VI/O = 200 mV+200 mVPP (differential)
f = 100 kHz		 -0.65 dB
COFF Off capacitance VDD = 1.65 V to 5.5 V
OE = 0 V, VDD
SEL = 0 V, VDD
Dn, CLKn, DAn, DBn, CLKAn, CLKBn = 0 V, 0.2 V
f = 1250 MHz		 1.5 pF
CON On capacitance VDD = 1.65 V to 5.5 V
OE = 0 V
SEL = 0 V, VDD
Dn, CLKn, DAn, DBn, CLKAn, CLKBn = 0 V, 0.2 V
f = 1250 MHz		 1.5 pF
DIGITAL CHARACTERISTICS
VIH Input logic high (SEL, OE) VI/O = 0.6 V RL = 50 Ω, CL = 5 pF 1.425 5.5 V
VIL Input logic low (SEL, /OE) VI/O = 0.6 V RL = 50 Ω, CL = 5 pF 0 0.5 V
IIH Input high leakage current (SEL, /OE) VI/O = 0.6 V RL = 50 Ω, CL = 5 pF -5 5 µA
IIL Input low leakage current (SEL, /OE) VI/O = 0.6 V RL = 50 Ω, CL = 5 pF -5 5 µA
RPD Internal pull-down resistance on digital input pins VI/O = 0.6 V RL = 50 Ω, CL = 5 pF 6 MΩ
CI Digital Input capacitance (SEL, /OE) f = 1 MHz 5 pF
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