9.2.3.1 MIPI D-PHY Application

The clock and data lanes can be interchanged as necessary to facilitate the best layout possible for the application. In addition, the signal lines of the TS5MP646 are routed single ended on the chip die. This makes the device suitable for both differential and single-ended high-speed systems. This also allows the positive and negative lines to be interchanged as necessary to facilitate the best layout possible for the application.

D-PHY application includes a differential clock and 4 differential datalanes. All the channels of the device perform similar and the clock or data signals may be interchanged as necessary to facilitate the best layout possible for the application.

Figure 29. MIPI D-PHY Example Pinout